IA186EM/IA188EM
8-Bit/16-Bit Microcontrollers
Data Sheet
February 25, 2011
Table 63. Interrupt Status Register (Slave Mode)
15
DHLT
14
13
12
11
10 9 8
Reserved
7
6
5
4
3
2
1
0
TMR2–TMR0
Bit [15]—DHLT DMA Halt → DMA activity is halted when this bit is 1. It is set to 1
automatically when any non-maskable interrupt occurs and is cleared to 0 when an IRET
instruction is executed.
Bits [14–3]—Reserved.
Bits [2–0]—TMR2–TMR0 Timer Interrupt Request → A pending interrupt request is
indicated by the respective timer, when any of these bits is 1.
Note: The TMR bit in the REQST register is a logical OR of these timer
interrupt requests.
5.1.42 REQST (02eh) (Master Mode)
Interrupt REQueST Register. This is a read-only register and such a read results in the status of
the interrupt request bits presented to the interrupt controller. The REQST register is undefined
on reset (see Table 64).
Table 64. Interrupt Request Register (Master Mode)
15
14 13 12
Reserved
11
10
SP0
9
WD
8
7
6 5
I4–I0
4
3
2
D1–D0
1
Reserved
0
TMR
Bits [15–11]—Reserved.
Bit [10]—SP0 Serial Port 0 Interrupt Request → This is the serial port interrupt state and
when enabled is the logical OR of all the serial port 0 interrupt sources, THRE, RDR,
BRKI, FER, PER, and OER.
Bit [9]—WD Watchdog Timer Interrupt Request → When it is a 1, the watchdog
interrupt state indicates that an interrupt is pending.
Bits [8–4]—I4–I0 Interrupt Requests → Setting any of these bits to 1 indicates that the
relevant interrupt has a pending interrupt.
Bits [3–2]—D1–D0 DMA Channel Interrupt Request → Setting either bit to 1 indicates
that the respective DMA channel has a pending interrupt.
Bit [1]—Reserved.
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