IA186ES/IA188ES
8-Bit/16-Bit Microcontrollers
Data Sheet
November 15, 2011
Bit [1]—Reserved.
Bit [0]—TMR Timer Interrupt Request → This is the timer interrupt state and is the
logical OR of the timer interrupt requests. When set to 1, it indicates that the timer
control unit has a pending interrupt.
5.1.45 REQST (02eh) (Slave Mode)
This read-only register results in the status of interrupt request bits being presented to the
interrupt controller. The status of these bits is available when this register is read. This register
is read-only.
When an internal interrupt request (D1/I6, D0/I5, TMR2, TMR1, or TMR0) occurs, the
respective bit is set to 1. The internally generated interrupt acknowledge resets these bits. The
REQST register contains 0000h on reset (see Table 66).
Table 66. Interrupt Request Register (Slave Mode)
15
14
13
12 11 10
Reserved
9
8
7
6
5
TMR2
4
TMR1
3
D1/I6
2
D0/I5
1
Res
0
TMR0
Bits [15–6]—Reserved.
Bit [5]—TMR2 Interrupt Requests → When set to 1, it indicates that Timer2 has a
pending interrupt.
Bit [4]—TMR1 Interrupt Requests → When set to 1, it indicates that Timer1 has a
pending interrupt.
Bit [3]—D1/I6 DMA Channel 1/Interrupt 6 Request → When set to 1, it indicates that
either the DMA channel 1 or int6 has a pending interrupt.
Bit [2]—D0/I5 DMA Channel 0/Interrupt 5 Request → When set to 1, it indicates that
either the DMA channel 0 or int5 has a pending interrupt.
Bit [1]—Reserved.
Bit [0]—TMR0 Timer Interrupt Request → When set to 1, it indicates that Timer0 has a
pending interrupt.
5.1.46 INSERV (02ch) (Master Mode)
IN-SERVice Register. The interrupt controller sets the bits in this register when the interrupt is
taken. The INSERV register contains 0000h on reset (see Table 67).
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