IA186ES/IA188ES
8-Bit/16-Bit Microcontrollers
Data Sheet
November 15, 2011
Bit [4]—TMR1 Timer1 Interrupt Mask → This bit provides the state of the mask bit in
the Timer Interrupt Control register. When set to 1, it indicates that the interrupt request
is masked.
Bit [3]—D1/I6 DMA Channel Interrupt 6 Mask → This bit provides the state of the mask
bit in the DMA channel 0 or int5 Interrupt Control register. When set to 1, it indicates
that the interrupt request is masked.
Bit [2]—D0/I5 DMA Channel Interrupt 5 Mask → This bit provides the state of the mask
bit in the DMA channel 1 or int6 Interrupt Control register. When set to 1, it indicates
that the interrupt request is masked.
Bit [0]—TMR0 Timer Interrupt Mask → This bit provides the state of the mask bit in the
Timer Interrupt Control register. When set to 1, it indicates that the interrupt request is
masked.
5.1.51 POLLST (026h) (Master Mode)
POLL STatus Register. This register reflects the current state of the poll register and can be read
without affecting its contents. However, the current interrupt is acknowledged and replaced by
the next interrupt when the poll register is read. The poll status register is read-only (see
Table 72).
Table 72. POLL Status Register
15
IREQ
14
13
12
11 10 9
Reserved
8
7
6
5
4
3 2 1
S4–S0
0
Bit [15]—IREQ Interrupt Request → This bit is set to 1 when an interrupt is pending and
during this state, the S4–S0 bits contain valid data.
Bits [14–6]—Reserved.
Bit [5–0]—S [5–0] Poll Status → These bits show the interrupt type of the highest
priority pending interrupt.
5.1.52 POLL (024h) (Master Mode)
POLL Register. The current interrupt is acknowledged and replaced by the next interrupt when
the poll register is read. The poll status register reflects the current state of the poll register and
can be read without affecting its contents. The poll register is read-only (see Table 73).
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