IA6805E2
Microprocessor Unit
As of Production Version 00
29 August 2007
Registers:
The following paragraphs describe the registers contained in the MPU. Figure 6 shows the
programming model and Figure 7 shows the interrupt stacking order.
7
A
7
X
12
PCH
12
0
6
1
8
7
PCL
0
ACCUMULATOR
0
INDEX REGISTER
0
PROGRAM COUNTER
0
SP
STACK POINTER
0
0
0
0
0
4
H
I
CC
N
Z
0
C
CONDITION CODE REGISTER
CARRY/BORROW
ZERO
NEGATIVE
INTERRUPT MASK
HALF CARRY
Figure 6. Programming Model
NOTE: Since the stack pointer decrements during pushes, the PCL is stacked first,
followed by PCH, etc. Pulling from the stack is in the reverse order.
STACK
1
R
E
T
U
R
N
1
1
CONDITION CODE
REGISTER
I
N
T
E
R
R
U
P
T
ACCUMULATOR
INDEX REGISTER
0
0
0
PCL
PCH
INCREASING MEMORY
ADDRESSES
DECREASING MEMORY
ADDRESSES
UNSTACK
Figure 7. Interrupt Stacking Order
Copyright
©
2007
©
IA211081401-03
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