IA21140AF
Preliminary Data Sheet
PCI FAST ETHERNET LAN CONTROLLER
PCI Other Signals:
Timing Diagram
clk
Tval (max)
Tval (min)
Vtest*
output
Ton
Toff
input
Tsu
Th
Note: Vtest is 1.5 V in a 5.0 V signaling environment and is
0.4 * vdd_clamp in a 3.3 V signaling environment.
Timing Characteristics
Symbol
Tval
Ton
Toff
Tsu
Th
Parameter
clk-to-signal valid delay
Float-to-active delay from clk
Active -to-float delay from clk
Input signal valid setup time before clk
Input signal hold time from clk
Min
2
2
-
7
0
Max
11
-
28
-
-
Unit
ns
ns
ns
ns
ns
Copyright
©
2001
ENG210010110-00
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