IA21140AF
Preliminary Data Sheet
PCI FAST ETHERNET LAN CONTROLLER
MII/SYM Port Timing Waveforms:
Transmit:
Timing Diagram
Tcc
Tcr
Tch
mii_sym_tclk
Trv
mii_sym_txd[3:0]
Trh
mii_sym_txen
Tcf
Tcl
Timing Characteristics
Symbol
Tcc
Tch
Tcl
Tcr
Tcf
Trv
Trh
•
Definition
mii_sym_tclk cycle time (±50 ppm)
mii_sym_tclk high time
mii_sym_tclk low time
mii_sym_tclk rise time
mii_sym_tclk fall time
mii_ tclk rise to mii_txen valid time
mii_sym_tclk rise to mii_sym_txd valid time
mii_txen hold after mii_tclk rise time
or
Min*
-
14t
14t
-
-
-
5
Typ*
40t
-
-
8
8
-
-
Max*
-
26t
26t
-
-
20
-
Units
ns
ns
ns
ns
ns
ns
ns
t = 1 for 100 Mbps operation and t = 10 for 10 Mbps operation.
Copyright
©
2001
ENG210010110-00
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