Page 9 of 32
IA80C152
Preliminary Data Sheet
UNIVERSAL COMMUNICATIONS CONTROLLER
Item
52.
53.
54.
55.
56.
57.
58.
Register
Name
TFIFO
TH0
TH1
TL0
TL1
TMOD
TSTAT
Register
Address
085h
08Ch
08Dh
08Ah
08Bh
089h
0D8h
Table 4 - SFR Summary
Functional
Block
Description
GSC
Transmit FIFO
C8051
Timer (High) 0
C8051
Timer (High) 1
C8051
Timer (Low) 0
C8051
Timer (Low) 1
C8051
Timer Mode
GSC
Transmit Status
Initial
Value
X
00h
00h
00h
00h
00h
XX000100b
Interrupt
Priority
-
1
2
3
4
5
6
7
8
9
10
11
Table 5 - Interrupt Summary
Priority
Enable
Interrupt
Symbol
Symbol
Priority
Name
Name
Name
Address
Enable All Interrupts
-
EA
-
External Interrupt 0
PX0
EX0
0B8h
GSC Receive Valid
PGSRV
EGSRV
0F8h
Timer 0 Overflow
PT0
ET0
0B9h
GSC Receive Error
PGSRE
EGSRE
0F9h
DMA Channel 0 Done
PDMA0
EDMA0
0FAh
External Interrupt 1
PX1
EX1
0BAh
GSC Transmit Valid
PGSTV
EGSTV
0FBh
DMA Channel 1 Done
PDMA1
EDMA1
0FCh
Timer 1 Overflow
PT1
ET1
0BBh
GSC Transmit Error
PGSRE
EGSRE
0FDh
UART Transmit/Receive
PS
ES
0BCh
Enable
Address
0AFh
0A8h
0C8h
0A9h
0C9h
0CAh
0AAh
0CBh
0CCh
0ABh
0CDh
0ACh
Vector
Address
-
03h
2Bh
0Bh
33h
3Bh
13h
43h
53h
1Bh
4Bh
23h
Power Conservation Modes
There are 2 power conservation modes identified as Idle Mode and Power Down Mode. The
IA80C152 pins will have values according to the Table 6 below.
Idle Mode is entered through software control of the PCON register. Idle halts processor
execution and the DMA. The GSC continue to operate to the extent that it can without the
processor or DMA servicing its requests. Idle mode is exited upon receipt of any enabled interrupt
or invoking a hardware reset.
Power Down Mode is entered through software control of the PCON register. Power Down
disables the oscillator causing all functions to stop. RAM data is maintained since power is not
removed from the device. The only way to exit power down mode is to invoke a hardware reset.
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2000
innovASIC
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