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IA80C152
Preliminary Data Sheet
UNIVERSAL COMMUNICATIONS CONTROLLER
80C152 Register Set Descriptions
The following are detailed descriptions for the IA80C152 register set. This register set is the same
for all versions of the IA80C152. There is no difference between the IA80C152 register set and the
register set for the original device.
In addition to the registers listed below, there are four banks of eight general purpose registers (R0
through R7) which reside within internal RAM space. Selection of these register banks is controlled
through the Program Status Word (PSW).
The register descriptions are listed in alphanumeric order. The asterisk (*) indicates the register is bit
addressable.
A* (0E0h)
- Accumulator register used for various memory, arithmetic, and logic operations.
ADR0,1,2,3 (095h, 0A5h, 0B5h, 0c5h)
- Address match registers contain the values which determine which data will be
accepted as valid. If using 8 bit addressing mode a match with any of the four registers will cause the data to be accepted.
If using 16 bit addressing mode a match with the pairs ADR1 and ADR2 or ADR3 and ADR2 will cause the data to be
accepted. A received address of all 1s will be accepted regardless of whether the address mode is 16 bit or 8 bit.
B* (0F0h)
- B register used for multiply and divide instructions. May also be used as a general purpose register.
AMSK0,1 (0D5h, 0E5h)
- Address Match Mask registers are used to set the corresponding bit in Address match registers
to don’ care. Setting the bit to a one in the AMSK register sets the corresponding bit in the ADR register to don’ care.
t
t
BAUD (094h)
- Contains the value to be used by the baud rate determining equation. The value written to BAUD will
actually be stored in a reload register. When the BAUD register contents are decremented to 00H the BAUD register will
be reloaded from the reload register. Reading the BAUD register yields the current baud rate timer value. A read during a
GSC operation may not give the current value since the value in BAUD could decrement after it is read and before the
read value can be stored in its destination.
BCRL0, BCRH0 (0E2h, 0E3h)
- Byte count register high and low bytes for DMA channel 0. The two registers provide
a 16-bit value representing for the number of DMA transfers via channel 0. Valid count range is from 0 to 65535.
BCRL0, BCRH0 (0F2h, 0F3h)
- Byte count register high and low bytes for DMA channel 1. The two registers provide
a 16-bit value representing for the number of DMA transfers via channel 1. Valid count range is from 0 to 65535.
BKOFF (0C4h)
- An 8 bit count down timer with a clock period equal to one slot time. A user may read the register, but
the register is clocked asynchronously to the CPU so invalid data can result. Writing to BKOFF will have no effect.
DARL0, DARH0 (0C2h, 0C3h)
- Destination address register high and low bytes for DMA channel 0. The two
registers provide a 16-bit value representing the address of the destination for a DMA transfer via channel 0. Valid
address range is from 0 to 65535.
DARL0, DARH0 (0D2h, 0D3h)
- Destination address register high and low bytes for DMA channel 1. The two
registers provide a 16-bit value representing the address of the destination for a DMA transfer via channel 1. Valid
address range is from 0 to 65535.
DCON0,1 (092h, 093h)
- DCON0 and DCON1 control DMA channel 0 or 1, respectively. Each bit in these 8-bit
registers control the DMA transfer as described below.
7
DAS
6
IDA
5
SAS
4
ISA
3
DM
2
TM
1
DONE
0
GO
DAS
- This bit in conjunction with IDA determine the destination address space.
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