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IN74AC112D 参数 Datasheet PDF下载

IN74AC112D图片预览
型号: IN74AC112D
PDF下载: 下载PDF文件 查看货源
内容描述: 双JK触发器具有​​置位和复位高速硅栅CMOS [Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS]
分类和应用: 触发器
文件页数/大小: 5 页 / 179 K
品牌: INTEGRAL [ INTEGRAL CORP. ]
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IN74AC112
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF,Input t
r
=t
f
=3.0 ns)
V
CC*
Symbol
Parameter
V
Guaranteed Limits
25
°C
Min
f
max
t
PLH
t
PHL
t
PLH
t
PHL
C
IN
Maximum Clock Frequency (Figure 1)
Propagation Delay, Clock to Q or Q
(Figure 1)
Propagation Delay, Clock to Q or Q
(Figure 1)
Propagation Delay, Set or Reset to Q or Q
(Figure 2)
Propagation Delay, Set or Reset to Q or Q
(Figure 2)
Maximum Input Capacitance
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
5.0
145
145
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
4.5
16.0
13.0
16.0
13.0
11.0
9.5
11.0
9.5
Max
-40°C to
85°C
Min
125
125
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
4.5
17.0
13.5
16.5
13.5
11.5
10.0
11.5
10.0
Max
MHz
ns
ns
ns
ns
pF
Unit
Typical @25°C,V
CC
=5.0 V
C
PD
*
Power Dissipation Capacitance
35
pF
Voltage Range 3.3 V is 3.3 V
±0.3
V
Voltage Range 5.0 V is 5.0 V
±0.5
V
TIMING REQUIREMENTS
(C
L
=50pF,Input t
r
=t
f
=3.0 ns)
V
CC*
Symbol
t
su
t
h
t
w
t
w
t
rec
*
Guaranteed Limits
25
°C
6.5
4.5
0
0
6.0
5.0
6.5
5.0
0
0
-40°C to
85°C
7.5
5.0
0
0
6.5
5.5
7.5
5.5
0
0
Unit
ns
ns
ns
ns
ns
Parameter
Minimum Setup Time, J or K to Clock (Figure
3)
Minimum Hold Time, Clock to J or K (Figure
3)
Minimum Pulse Width, Clock (Figure 1)
Minimum Pulse Width,Set or Reset
(Figure 2)
Minimum Recovery Time, Set or Reset to
Clock (Figure 2)
V
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
Voltage Range 3.3 V is 3.3 V
±0.3
V
Voltage Range 5.0 V is 5.0 V
±0.5
V
130