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82547EI 参数 Datasheet PDF下载

82547EI图片预览
型号: 82547EI
PDF下载: 下载PDF文件 查看货源
内容描述: DUAL足迹 [Dual Footprint]
分类和应用:
文件页数/大小: 66 页 / 856 K
品牌: INTEL [ INTEL CORPORATION ]
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82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide
4.1.7
Impedance Discontinuities
Impedance discontinuities cause unwanted signal reflections. Avoid vias (signal through holes) and
other transmission line irregularities. If vias must be used, a reasonable budget is two per
differential trace. Unused pads and stub traces should also be avoided.
4.1.8
Reducing Circuit Inductance
Traces should be routed over a continuous ground plane with no interruptions. If there are vacant
areas on a ground or power plane, the signal conductors should not cross the vacant area. This
increases inductance and associated radiated noise levels. Noisy logic grounds should be separated
from analog signal grounds to reduce coupling. Noisy logic grounds can sometimes affect sensitive
DC subsystems such as analog to digital conversion, operational amplifiers, etc. All ground vias
should be connected to every ground plane; and similarly, every power via, to all power planes at
equal potential. This helps reduce circuit inductance. Another recommendation is to physically
locate grounds to minimize the loop area between a signal path and its return path. Rise and fall
times should be as slow as possible. Because signals with fast rise and fall times contain many high
frequency harmonics, which can radiate significantly. The most sensitive signal returns closest to
the chassis ground should be connected together. This will result in a smaller loop area and reduce
the likelihood of crosstalk. The effect of different configurations on the amount of crosstalk can be
studied using electronics modeling software.
4.1.9
Signal Isolation
To maintain best signal integrity, keep digital signals far away from the analog traces. A good rule
of thumb is no digital signal should be within 300 mils (7.5 mm) of the differential pairs. If digital
signals on other board layers cannot be separated by a ground plane, they should be routed at right
angles with respect to the differential pairs. If there is another LAN controller on the board, take
care to keep the differential pairs from that circuit away.
Some rules to follow for signal isolation:
Separate and group signals by function on separate layers if possible. Maintain a gap of 100
mils between all differential pairs (Ethernet) and other nets, but group associated differential
pairs together. Note: Over the length of the trace run, each differential pair should be at least
0.3 inches away from any parallel signal traces.
Physically group together all components associated with one clock trace to reduce trace
length and radiation.
Isolate I/O signals from high-speed signals to minimize crosstalk, which can increase EMI
emission and susceptibility to EMI from other signals.
Avoid routing high-speed LAN traces near other high-frequency signals associated with a
video controller, cache controller, processor, or other similar devices.
4.1.10
Power and Ground Planes
Good grounding requires minimizing inductance levels in the interconnections and keeping ground
returns short, signal loop areas small, and power inputs bypassed to signal return, will significantly
reduce EMI radiation.
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