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82547EI 参数 Datasheet PDF下载

82547EI图片预览
型号: 82547EI
PDF下载: 下载PDF文件 查看货源
内容描述: DUAL足迹 [Dual Footprint]
分类和应用:
文件页数/大小: 66 页 / 856 K
品牌: INTEL [ INTEL CORPORATION ]
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82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide
Layer 3 is used for power planes.
Layer 4 is a signal layer. For Gigabit designs, it is common to route two of the differential pairs
on this layer.
This board stack up configuration can be adjusted to conform to your company's design rules.
4.1.4
Differential Pair Trace Routing
Trace routing considerations are important to minimize the effects of crosstalk and propagation
delays on sections of the board where high-speed signals exist. Signal traces should be kept as short
as possible to decrease interference from other signals, including those propagated through power
and ground planes. Observe the following suggestions to help optimize board performance:
Maintain constant symmetry and spacing between the traces within a differential pair.
Keep the signal trace lengths of a differential pair equal to each other.
Keep the total length of each differential pair under four inches. Designs with differential
traces longer than 5 inches are much more likely to have degraded receive Bit Error Rate
(BER) performance, IEEE PHY conformance failures, and/or excessive Electromagnetic
Interference (EMI) radiation
Do not route the transmit differential traces closer than 100 mils to the receive differential
traces.
Do not route any other signal traces both parallel to the differential traces, and closer than 100
mils to the differential traces (300 mils is recommended).
Keep maximum separation within differential pairs to seven mils.
For high-speed signals, the number of corners and vias should be kept to a minimum. If a 90°
bend is required, it is recommended to use two 45° bends instead. See
Traces should be routed away from board edges by a distance greater than the trace height
above the ground plane. This allows the field around the trace to couple more easily to the
ground plane rather than to adjacent wires or boards.
Do not route traces and vias under crystals or oscillators. This will prevent coupling to or from
the clock. And as a general rule, place traces from clocks and drives at a minimum distance
from apertures by a distance that is greater than the largest aperture dimension.
45°
45°
Figure 6. Trace Routing
23