Networking Silicon — 82551IT
All accesses, either read or write, are preceded by a command instruction to the device. The
address field is six bits for a 64-register EEPROM or eight bits for a 256-register EEPROM. The
end of the address field is indicated by a dummy zero bit from the EEPROM, which indicates the
entire address field has been transferred to the device. An EEPROM read instruction waveform is
shown in the figure below.
Figure 10. 64-Word EEPROM Read Instruction Waveform
EESK
EECS
A5
A4
A2
AA
A0
A3
10
EEDI
READ OP code
D0
D15
EEDO
The 82551IT performs an automatic read of four words (0h, 1h, 2h, and Ah) of the EEPROM after
the de-assertion of Reset. Refer to the 82551QM/ER/IT EEPROM Map and Programming
Information for more details.
Datasheet
31
INTEL [ INTEL ]
