82551IT 参数 Datasheet PDF下载

82551IT — Networking Silicon

5.7

Media Independent Interface (MII) Management Interface

The MII management interface allows the CPU to control the PHY unit through a control register

in the 82551IT. This allows the software driver to place the PHY in specific modes such as full

duplex, loopback, power down, etc., without the need for specific hardware pins to select the

desired mode. This structure allows the 82551IT to query the PHY unit for status of the link. This

register is the MDI Control Register and resides at offset 10h in the 82551IT CSR. (The MDI

registers are described in detail in

The CPU writes commands

to this register and the 82551IT reads or writes the control/status parameters to the PHY unit

through the MDI register. Although the 82551IT follows the MII format, the MI bus is not

accessible on external pins.

34

Datasheet