Networking Silicon — 82551QM
2.0
Architectural Overview
The Intel
®
82551QM is divided into five main subsystems: a parallel subsystem, a FIFO
subsystem, the manageability subsystem, a 10/100 Mbps Carrier Sense Multiple Access with
Collision Detect (CSMA/CD) unit, and a 10/100 Mbps physical layer (PHY) unit.
2.1
Parallel Subsystem Overview
The parallel subsystem is comprised of several functional blocks: a PCI bus master interface, a
micromachine processing unit and its corresponding microcode ROM, and a PCI Target Control/
Flash/EEPROM/Modem interface. The parallel subsystem also interfaces to the FIFO subsystem,
passing data (such as transmit, receive, and configuration data) and command and status
parameters between these two blocks.
The dual function modem and PCI bus master interface provides a complete glueless interface to a
PCI bus and is compliant with the PCI Bus Specification, Revision 2.2. The 82551QM provides 32
bits of addressing and data, as well as the PCI control interface. As a PCI target, it conforms to the
PCI configuration scheme, which allows all accesses to the 82551QM to be automatically mapped
into free memory and I/O space upon initialization of a PCI system. When transmit and receive
data is processed, the 82551QM operates as a master on the PCI bus, initiating zero wait state
transfers.
The 82551QM Control/Status Register Block is part of the PCI target element. The Control/Status
Register block consists of the following 82551QM internal control registers: System Control Block
(SCB), PORT, Flash Control, EEPROM Control, Modem Control and Management Data Interface
(MDI) Control.
An embedded micromachine consisting of independent transmit and receive processing units allow
the 82551QM to execute commands and receive incoming frames with no real time CPU
intervention.
The 82551QM contains a multiplexed interface to connect an external serial EEPROM and Flash
memory and modem. The Flash interface, which can also be used to connect to any standard 8-bit
device, provides up to 128 KB of addressing to the Flash. Both read and write accesses are
supported. The Flash can be used for remote boot functions, network statistical and diagnostics
functions, and management functions. The Flash is mapped into host system memory (anywhere
within the 32-bit memory address space) for software accesses. It is also mapped into an available
boot expansion ROM location during boot time of the system. More information on the Flash
interface is detailed in
The serial EEPROM is used
to store relevant information for a LAN connection such as node address, as well as board
manufacturing and configuration information. Both read and write accesses to the EEPROM are
supported by the 82551QM. Information on the EEPROM interface is detailed in
The modem interface uses an ISA-like signal and is described in
more detail in
Datasheet
3
INTEL [ INTEL CORPORATION ]
