82562ET — Networking Silicon
Pin Name
ISOL_TEX
Pin
Number
29
I
Type
Description
Test Execute.
The Test Execute signal sets the device into asynchronous
test mode in conjunction with the Test Clock, Test Input, and Test Enable
pins (refer to
In the manufacturing test mode, it places the command that was entered
through the TI pin in the instruction register.
Note: ISOL_TEX has an internal pull-down resistor.
TOUT
TESTEN
26
21
O
I
Test Output.
The Test Output pin is used for Boundary XOR scan output.
In the manufacturing test mode, it acts as the test output port.
Test Enable.
The Test Enable pin is used to enable test mode and should
be pulled down to V
SS
to allow XOR Tree test mode.
3.8
Power and Ground Connections
Pin Name
VCC
VCCP
VCCA
VCCA2
VCCT
VSS
VSSP
VSSA
VSSA2
VCCR
VSSR
Pin
Number
1, 25
36, 40
2,
7,
9, 12,
14, 17
8, 13, 18 DPS
24, 48
33, 38
3
6
19, 23
20, 22
APS
APS
Analog Power.
Analog Ground.
These pins should not be isolated from the main digital.
Digital Ground.
These pins should be connected to the main digital
ground.
Type
DPS
Description
Digital 3.3 V Power.
These pins should be connected to the main digital
power supply.
8
Datasheet
INTEL [ INTEL CORPORATION ]
