Networking Silicon — 82562ET
2.0
82562ET Architectural Overview
The 82562ET is a highly integrated Platform LAN Connect device that combines a 10BASE-T and
100BASE-TX physical layer interfaces. The 82562ET supports a single interface fully compliant
with the IEEE 802.3 standard.
provides a block diagram of the 82562ET architecture.
Figure 1. 82562ET Block Diagram
Digital
Equalizer
Adaptation
Equalizer &
BLW correction
MDI/MDI-X
CRS/Link 10
Detection
Transmit DAC
10/100
Auto-
Negotiation
Bias & Band-
Gap Voltage
Circuit
Clock
Generator
Control
Registers
Digital Clock
Recovery (100)
Digital Clock
Recovery (10)
100Base-TX
PCS
Port LED
Drivers
LILED
ACTLED
SPEEDLED
RDN/RDP
LAN_RSTSYNC
10Base-T
PCS
LAN
Connect
Interface
3
3
LAN_TXD[2:0]
LAN_RXD[2:0]
LAN_CLK
TDN/ TDP
X1
Crystal
25 MHz
X2
The 8252ET is a 3.3 V device in a 48-pin Shrink Small Outline Package (SSOP). This document
describes the architecture of the device in all modes of operation.
Four pins, test Enable (TESTEN), Test Clock (ISOL_TCK), Test Input (ISOL_TI), and Test
Execute (ISOL_EX), define the general operation of the device.
shows the pin settings for
the different modes of operation.
Table 1.
82562ET Hardware Configuration
Mode of Operation
Normal operating
mode
Isolate mode
(Tri-state and full
power-down mode)
1
XOR Tree
1
0
0
0
1
1
1
TESTEN
0
ISOL_TCK
0
ISOL_TI
0
ISOL_EX
0
Comments
The ISOL_TCK, ISOL_TI,
and ISOL_EX pins can
remain floating.
The device is in tri-state
and power-down mode.
The device is in tri-state
and the fully powered
down.
The XOR Tree is used for
board testing and tri-state
mode.
0
1
1
1
NOTE:
Combinations not shown in
are reserved and should not be used.
Datasheet
3
INTEL [ INTEL CORPORATION ]
