Networking Silicon — 82562ET
Revision History
Revision
1.3
1.2
Revision Date
March 2003
October 2001
Description
Added product ordering code in Section 1.0.
Removed confidential status.
• Removed sections: “Physical Layer Interface Functionality” and “Platform
LAN Connect”.
• Changed “Electrical and Timing Specifications” section to “Voltage and Tem-
perature Specifications” and removed timing specifications.
Advance Information Datasheet release (Intel Confidential).
• On cover page, replaced Boundary Scan Support with XOR tree mode sup-
port. Added bullet for LAN Connect I/F.
• Pg. 3, added a Solution Block Diagram as included in OR-2338 Pg. 4 but
replaced EM with ET in diagram.
• Pg. 11, removed Figure 4, “NRZ to MLT-3 Encoding Diagram”.
• Pg. 35, changed the Rev. number on the 82562 Pinout symbol to 1.0.
Advance Information Datasheet release (Intel Secret).
• Modified Table 1 “82562ET Hardware Configuration” to add one row for XOR
Tree and include column for comments.
• Updated the descrition of the Activity LED signal in Section 3.6, “LED Pins”.
• Revised Section 3.7, “Miscellaneous Control Pins” to reflect references to
• Replaced diagrams in Section 5.1, “Package Information”.
• Corrected Figure 4 “NRZ to MLT-3 Encoding Diagram on Pg. 11 to reflect
correct signal transitions.
• Removed “10BASE-T Error Detection and Reporting” section since the
82562 does not do 10BASE-T error reporting.
Initial release.
1.1
June 2000
1.0
May 2000
0.6
Nov. 1999
0.55
Sept. 1999
Datasheet
iii
INTEL [ INTEL CORPORATION ]
