28F320J5 and 28F640J5
Three CE pins are used to enable and disable the device. A unique CE logic design (see
reduces decoder logic typically required for multi-chip
designs. External logic is not required when designing a single chip, a dual chip, or a 4-chip
miniature card or SIMM module.
The BYTE# pin allows either x8 or x16 read/writes to the device. BYTE# at logic low selects 8-bit
mode; address A
0
selects between the low byte and high byte. BYTE# at logic high enables 16-bit
operation; address A
1
becomes the lowest order address and address A
0
is not used (don’t care). A
device block diagram is shown in
When the device is disabled (see
and the RP# pin is at V
CC
, the standby mode
is enabled. When the RP# pin is at GND, a further power-down mode is enabled which minimizes
power consumption and provides write protection during reset. A reset time (t
PHQV
) is required
from RP# switching high until outputs are valid. Likewise, the device has a wake time (t
PHWL
)
from RP#-high until writes to the CUI are recognized. With RP# at GND, the WSM is reset and the
status register is cleared.
The Intel StrataFlash memory devices are available in several package types. The 64-Mbit is
available in 56-lead SSOP (Shrink Small Outline Package) and µBGA* package (micro Ball Grid
Array). The 32-Mbit is available in 56-lead TSOP (Thin Small Outline Package) and 56-lead
SSOP. Figures 2, 3, and 4 show the pinouts.
Figure 1. Intel StrataFlash
®
Memory Block Diagram
DQ
0
- DQ
15
V
CCQ
Output Buffer
Input Buffer
Query
Output
Multiplexer
Write Buffer
Data
Register
I/O Logic
CE
Logic
V
CC
BYTE#
CE
0
CE
1
CE
2
WE#
OE#
RP#
Identifier
Register
Status
Register
Command
User
Interface
Multiplexer
Data
Comparator
32-Mbit: A
0
- A
21
64-Mbit: A
0 -
A
22
Y-Decoder
Input Buffer
Y-Gating
Write State
Machine
32-Mbit: Thirty-two
64-Mbit: Sixty-four
128-Kbyte Blocks
Program/Erase
Voltage Switch
STS
V
PEN
V
CC
GND
Address
Latch
Address
Counter
X-Decoder
8
Datasheet
INTEL [ INTEL CORPORATION ]
