E
28F020
between the programmed byte and true data
means that the byte is successfully programmed.
Programming then proceeds to the next desired
byte location. Figure 4, the 28F020 Quick-Pulse
Programming Algorithm flowchart, illustrates how
commands are combined with bus operations to
perform byte programming. Refer to AC
Characteristics—Write/Erase/Program Only Oper-
ations and waveforms for specific timing
parameters.
a series of operations (pulses), along with byte
verification, to completely and reliably erase and
program the device.
2.2.4
QUICK-PULSE PROGRAMMING
ALGORITHM
The quick-pulse programming algorithm uses
programming operations of 10 µs duration. Each
operation is followed by a byte verification to
determine when the addressed byte has been
successfully programmed. The algorithm allows for
up to 25 programming operations per byte,
although most bytes verify on the first or second
operation. The entire sequence of programming
and byte verification is performed with VPP at high
voltage. Figure 4 illustrates the 28F020 Quick-
Pulse Programming Algorithm flowchart.
2.2.2.7
Reset Command
A Reset command is provided as a means to
safely abort the Erase or Program command
sequences. Following either Set-Up command
(Erase or Program) with two consecutive writes of
FFH will safely abort the operation. Memory
contents will not be altered. A valid command must
then be written to place the device in the desired
state.
2.2.5
QUICK-ERASE ALGORITHM
Intel’s quick-erase algorithm yields fast and reliable
electrical erasure of memory contents. The
algorithm employs a closed-loop flow, similar to the
quick-pulse programming algorithm, to simul-
taneously remove charge from all bits in the array.
2.2.3
EXTENDED ERASE/PROGRAM
CYCLING
EEPROM cycling failures have always concerned
users. The high electrical field required by thin
oxide EEPROMs for tunneling can literally tear
apart the oxide at defect regions. To combat this,
some suppliers have implemented redundancy
schemes, reducing cycling failures to insignificant
levels. However, redundancy requires that cell size
be doubled—an expensive solution.
Erasure begins with a read of memory contents.
The 28F020 is erased when shipped from the
factory. Reading FFH data from the device would
immediately be followed by device programming.
For devices being erased and reprogrammed,
uniform and reliable erasure is ensured by first
programming all bits in the device to their charged
state (Data = 00H). This is accomplished, using the
quick-pulse programming algorithm, in approxi-
mately four seconds.
Intel has designed extended cycling capability into
its ETOX flash memory technology. Resulting
improvements in cycling reliability come without
increasing memory cell size or complexity. First, an
advanced tunnel oxide increases the charge
carrying ability ten-fold. Second, the oxide area per
cell subjected to the tunneling electric field is one-
tenth that of common EEPROMs, minimizing the
probability of oxide defects in the region. Finally,
the peak electric field during erasure is
approximately 2 MV/cm lower than EEPROM. The
lower electric field greatly reduces oxide stress and
the probability of failure.
Erase execution then continues with an initial erase
operation. Erase verification (data = FFH) begins at
address 0000H and continues through the array to
the last address, or until data other than FFH is
encountered. With each erase operation, an
increasing number of bytes verify to the erased
state. Erase efficiency may be improved by storing
the address of the last byte verified in a register.
Following the next erase operation, verification
starts at that stored address location. Erasure
typically occurs in two seconds. Figure 5 illustrates
the 28F020 Quick-Erase Algorithm flowchart.
The 28F020 is capable of 100,000 program/erase
cycles. The device is programmed and erased
using Intel’s quick-pulse programming and quick-
erase algorithms. Intel’s algorithmic approach uses
13
INTEL [ INTEL ]
