28F008SA
Bus
Command
Comments
Operation
e
Address
erased
Write
Erase
Setup
Data
20H
e
Within block to be
e
D0H
Write
Erase
Data
e
Address
erased
Within block to be
Ý
Ready, V
or
Standby/Read
Check RY/BY
e
e
Busy
V
OH
OL
Read Status Register
Check SR.7
e
Toggle OE or CE to
e
Busy
1
Ready, 0
Ý
Ý
update Status Register
Repeat for subsequent bytes
Full status check can be done after each block or after a
sequence of blocks
290429–8
Write FFH after the last block erase operation to reset the
device to Ready Array Mode
FULL STATUS CHECK PROCEDURE
Bus
Command
Comments
Operation
Optional
Read
CPU may already have read
Status Register data in WSM
Ready polling above
Standby
Standby
Standby
Check SR.3
e
1
V
PP
Low Detect
Check SR.4,5
e
Both 1
Error
Command Sequence
Check SR.5
e
1
Block Erase Error
SR.3 MUST be cleared, if set during a block erase attempt,
before further attempts are allowed by the Write State
Machine
290429–9
SR.5 is only cleared by the Clear Status Register
Command, in cases where multiple blocks are erased
before full status is checked.
If error is detected, clear the Status Register before
attempting retry or other error recovery.
Figure 8. Automated Block Erase Flowchart
16
INTEL [ INTEL ]
