28F008SA
command (20H) is first written to the Command User
Interface followed by the Erase Confirm command
(D0H) These commands require both appropriate
sequencing and an address within the block to be
erased to FFH Block preconditioning erase and
verify are all handled internally by the Write State
Machine invisible to the system After the two-com-
mand erase sequence is written to it the 28F008SA
automatically outputs Status Register data when
read (see Figure 8 Block Erase Flowchart) The
CPU can detect the completion of the erase event
by analyzing the output of the RY BY pin or the
WSM Status bit of the Status Register
When erase is completed the Erase Status bit
should be checked If erase error is detected the
Status Register should be cleared The Command
User Interface remains in Read Status Register
mode until further commands are issued to it
This two-step sequence of set-up followed by execu-
tion ensures that memory contents are not acciden-
tally erased Also reliable block erasure can only
occur when V
PP
e
V
PPH
In the absence of this high
voltage memory contents are protected against era-
sure If block erase is attempted while V
PP
e
V
PPL
the V
PP
Status bit will be set to ‘‘1’’ Erase attempts
while V
PPL
k
V
PP
k
V
PPH
produce spurious results
and should not be attempted
Intelligent Identifier Command
The 28F008SA contains an Intelligent Identifier op-
eration initiated by writing 90H into the Command
User Interface Following the command write a read
cycle from address 00000H retrieves the manufac-
turer code of 89H A read cycle from address
00001H returns the device code of A2H To termi-
nate the operation it is necessary to write another
valid command into the register Like the Read Array
command the Intelligent Identifier command is func-
tional when V
PP
e
V
PPL
or V
PPH
Read Status Register Command
The 28F008SA contains a Status Register which
may be read to determine when a byte write or block
erase operation is complete and whether that oper-
ation completed successfully The Status Register
may be read at any time by writing the Read Status
Register command (70H) to the Command User In-
terface After writing this command all subsequent
read operations output data from the Status Regis-
ter until another valid command is written to the
Command User Interface The contents of the
Status Register are latched on the falling edge of
OE or CE whichever occurs last in the read cy-
cle OE or CE must be toggled to V
IH
before
further reads to update the Status Register latch
The Read Status Register command functions when
V
PP
e
V
PPL
or V
PPH
Erase Suspend Erase Resume
Commands
The Erase Suspend command allows block erase
interruption in order to read data from another block
of memory Once the erase process starts writing
the Erase Suspend command (B0H) to the Com-
mand User Interface requests that the WSM sus-
pend the erase sequence at a predetermined point
in the erase algorithm The 28F008SA continues to
output Status Register data when read after the
Erase Suspend command is written to it Polling the
WSM Status and Erase Suspend Status bits will de-
termine when the erase operation has been sus-
pended (both will be set to ‘‘1’’) RY BY will also
transition to V
OH
At this point a Read Array command can be written
to the Command User Interface to read data from
blocks other than that which is suspended The only
other valid commands at this time are Read Status
Register (70H) and Erase Resume (D0H) at which
time the WSM will continue with the erase process
The Erase Suspend Status and WSM Status bits of
the Status Register will be automatically cleared and
RY BY will return to V
OL
After the Erase Resume
command is written to it the 28F008SA automatical-
ly outputs Status Register data when read (see Fig-
ure 9 Erase Suspend Resume Flowchart) V
PP
must remain at V
PPH
while the 28F008SA is in Erase
Suspend
13
Clear Status Register Command
The Erase Status and Byte Write Status bits are set
to ‘‘1’’s by the Write State Machine and can only be
reset by the Clear Status Register Command These
bits indicate various failure conditions (see Table 4)
By allowing system software to control the resetting
of these bits several operations may be performed
(such as cumulatively writing several bytes or eras-
ing multiple blocks in sequence) The Status Regis-
ter may then be polled to determine if an error oc-
curred during that sequence This adds flexibility to
the way the device may be used
Additionally the V
PP
Status bit (SR 3) MUST be re-
set by system software before further byte writes or
block erases are attempted To clear the Status
Register the Clear Status Register command (50H)
is written to the Command User Interface The Clear
Status Register command is functional when V
PP
e
V
PPL
or V
PPH
Erase Setup Erase Confirm
Commands
Erase is executed one block at a time initiated by a
two-cycle command sequence An Erase Setup
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