28F008SA
Table 1 Pin Description
Symbol
A
0
–A
19
DQ
0
–DQ
7
Type
INPUT
INPUT OUTPUT
Name and Function
ADDRESS INPUTS
for memory addresses Addresses are internally
latched during a write cycle
DATA INPUT OUTPUTS
Inputs data and commands during Command
User Interface write cycles outputs data during memory array Status
Register and Identifier read cycles The data pins are active high and
float to tri-state off when the chip is deselected or the outputs are
disabled Data is internally latched during a write cycle
CHIP ENABLE
Activates the device’s control logic input buffers
decoders and sense amplifiers CE is active low CE high deselects
the memory device and reduces power consumption to standby levels
RESET DEEP POWERDOWN
Puts the device in deep powerdown
mode RP is active low RP high gates normal operation RP also
locks out block erase or byte write operations when active low providing
data protection during power transitions RP active resets internal
automation Exit from Deep Powerdown sets device to read-array mode
OUTPUT ENABLE
Gates the device’s outputs through the data buffers
during a read cycle OE is active low
WRITE ENABLE
Controls writes to the Command User Interface and
array blocks WE is active low Addresses and data are latched on the
rising edge of the WE pulse
READY BUSY
Indicates the status of the internal Write State
Machine When low it indicates that the WSM is performing a block
erase or byte write operation RY BY high indicates that the WSM is
ready for new commands block erase is suspended or the device is in
deep powerdown mode RY BY is always active and does
NOT
float
to tri-state off when the chip is deselected or data outputs are disabled
BLOCK ERASE BYTE WRITE POWER SUPPLY
for erasing blocks of
the array or writing bytes of each block
NOTE
With V
PP
k
V
PPLMAX
memory contents cannot be altered
DEVICE POWER SUPPLY (5V
g
10% 5V
g
5%)
GROUND
CE
INPUT
RP
INPUT
OE
WE
INPUT
INPUT
RY BY
OUTPUT
V
PP
V
CC
GND
4
INTEL [ INTEL CORPORATION ]
