28F008SA
PRINCIPLES OF OPERATION
FFFFF
The 28F008SA includes on-chip write automation to
manage write and erase functions The Write State
Machine allows for 100% TTL-level control inputs
fixed power supplies during block erasure and byte
write and minimal processor overhead with RAM-
like interface timings
After initial device powerup or after return from
deep powerdown mode (see Bus Operations) the
28F008SA functions as a read-only memory Manip-
ulation of external memory-control pins allow array
read standby and output disable operations Both
Status Register and intelligent identifiers can also be
accessed through the Command User Interface
when V
PP
e
V
PPL
This same subset of operations is also available
when high voltage is applied to the V
PP
pin In addi-
tion high voltage on V
PP
enables successful block
erasure and byte writing of the device All functions
associated with altering memory contents byte
write block erase status and intelligent identifier
are accessed via the Command User Interface and
verified thru the Status Register
Commands are written using standard microproces-
sor write timings Command User Interface contents
serve as input to the WSM which controls the block
erase and byte write circuitry Write cycles also inter-
nally latch addresses and data needed for byte write
or block erase operations With the appropriate com-
mand written to the register standard microproces-
sor read timings output array data access the intelli-
gent identifier codes or output byte write and block
erase status for verification
Interface software to initiate and poll progress of in-
ternal byte write and block erase can be stored in
any of the 28F008SA blocks This code is copied to
and executed from system RAM during actual flash
memory update After successful completion of byte
write and or block erase code data reads from the
28F008SA are again possible via the Read Array
command Erase suspend resume capability allows
system software to suspend block erase to read
data and execute code from any other block
F0000
EFFFF
E0000
DFFFF
D0000
CFFFF
C0000
BFFFF
B0000
AFFFF
A0000
9FFFF
90000
8FFFF
80000
7FFFF
70000
6FFFF
60000
5FFFF
50000
4FFFF
40000
3FFFF
30000
2FFFF
20000
1FFFF
10000
0FFFF
00000
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
Figure 6 Memory Map
Command User Interface and Write
Automation
An on-chip state machine controls block erase and
byte write freeing the system processor for other
tasks After receiving the Erase Setup and Erase
Confirm commands the state machine controls
block pre-conditioning and erase returning progress
via the Status Register and RY BY output Byte
write is similarly controlled after destination address
and expected data are supplied The program and
erase algorithms of past Intel flash memories are
now regulated by the state machine including pulse
repetition where required and internal verification
and margining of data
9
INTEL [ INTEL CORPORATION ]
