Dual-Speed Fast Ethernet Transceiver — LXT970A
3.3.7
Typical Application
is typical interface circuitry of the LXT970A. The diagram groups similar
pins; it does not portray the actual chip pinout. The Media Independent Interface (MII) pins are at
the upper left. Hardware Control Interface pins are center left. The line interface pins for twisted-
pair and fiber are shown on the top and bottom right respectively.
The VCCD and VCCIO pins are at the bottom of the diagram. VCCT, VCCR, and VCCA are at the
center right. All VCC pins (except VCCIO) use a single power supply. VCCIO may be powered by
a 3.3V supply, and may be separately connected.
3.3.7.1
Voltage Divider For MF Inputs
The LXT970A requires an external voltage divider to provide optional (V
MF
2 and V
MF
3) multi-
level inputs to the Multi-Function (MF) pins. These voltage levels are designated as V
MF
1 - V
MF
4.
A single voltage divider may be used to drive the MF pins in designs using multiple PHYs.
shows a voltage divider with three 1 k
Ω
resistors configured in series between VCC and
Ground.
Figure 20. Voltage Divider
1k
W
+5V
1k
W
1k
W
V
MF
1
V
MF
2
V
MF
3
V
MF
4
Datasheet
45
INTEL [ INTEL CORPORATION ]
