LXT970A — Dual-Speed Fast Ethernet Transceiver
Table 53. Interrupt Enable Register (Address 17, Hex 11)
Bit
Name
Description
Type 1
Default
17.15:4 Reserved
Write as 0; ignore on read.
R/W
N/A
1 = Reduced MII driver levels. Pull-down strength of the MII driver is
reduced by a factor of 10, and the pull-up strength is reduced by a factor
of 8. Reduced driver levels on the MII I/O pins are recommended for
managed multi-port applications.
MIIDRVLVL
17.3
R/W
R/W
0
0
0 = High-strength MII driver levels that can effectively source 50 - 60 mA.
Series termination resistors (55Ω) are recommended on all output
signals when using this level to avoid undershoot or overshoot.
1 = Enhanced link loss criteria. Link loss criteria is independent of symbol
error rate. Loss of scrambler lock for more than 1 - 2 msec will brings the
link down. Link up criteria is based on symbol error rate.
LNK
17.2
CRITERIA
0 = Standard link criteria. Both link up and link loss are based on symbol
error rate.
1 = Enable interrupts. Must be enabled for bit 17.0 or 19.12 to be
effective.
17.1
17.0
INTEN
TINT
R/W
R/W
0
0
0 = Disable interrupts.
1 = Forces MDINT Low and sets bit 18.15 = 1. Also forces interrupt
pulse on MDIO when bit 19.12 = 1.
0 = Normal operation.
This bit is ignored unless the interrupt function is enabled (17.1 = 1).
1. R/W = Read /Write
Table 54. Interrupt Status Register (Address 18, Hex 12)
Bit
Name
Description
Type 1
RO
Default
N/A
1 = Indicates MII interrupt pending.
18.15
MINT
0 = Indicates no MII interrupt pending. This bit is cleared by reading
Register 1 followed by reading Register 18.
1 = Indicates that the LXT970A is fully powered up and the on-chip clocks
are stable.
18.14
XTALOK
RO
RO
0
0
0 = Indicates that XTAL circuit is not stable.
Ignore
18.13:0
Reserved
1. RO = Read Only
70
Datasheet
INTEL [ INTEL ]
