Dual-Speed Fast Ethernet Transceiver — LXT970A
Table 55. Configuration Register (Address 19, Hex 13)
Bit
Name
Reserved
Description
Type 1
Default
19.15
Write as 0; ignore on read.
R/W
N/A
1 = 100BASE-T transmit test enabled, LXT970A transmits data
regardless of link status. This function is the analog of the link test
function (19.8) for 100BASE-TX.
Txmit Test
(100BASE-TX)
19.14
R/W
0
0 = Normal operation.
1 = Enable Repeater Mode.
0 = Enable DTE Mode.
19.13
19.12
Repeater Mode
MDIO_INT
R/W
R/W
Note 2
0
1 = Enable interrupt signaling on MDIO (if 17.1 = 1).
0 = Normal operation (MDIO Interrupt disabled).
Bit is ignored unless the interrupt function is enabled (17.1 = 1).
1 = Disable 10BT TP Loopback. Data transmitted by the MAC will not
loopback to the RXD, RX_DV, and CRS pins.
0 = Enable 10BT TP Loopback - Preamble, SFD, and data are directly
looped back to the MII.
TP Loopback
(10BASE-T)
19.11
R/W
0
SQE
1 = Enable SQE.
19.10
19.9
19.8
R/W
R/W
R/W
0
0
(10BASE-T)
0 = Disable SQE (Default).
Jabber
1 = Disable jabber.
(10BASE-T)
0 = Normal operation (jabber enabled).
Link Test
1 = Disable 10BASE-T link integrity test.
Note 3
(10BASE-T)
0 = Normal operation (10BASE-T link integrity test enabled).
Determine condition indicated by LEDC.
bit 7 bit 6 Description
0
0
1
1
0
1
0
1
LEDC indicates collision
LEDC is off
LEDC
Programming bits
19.7:6
R/W
0,0
LEDC indicates activity.
LEDC is continuously on (for diagnostic use).
1 = TX clock is advanced relative to TXD<4:0> and TX_ER by 1/2
TX_CLK cycle.
19.5
19.4
Advance TX Clock
R/W
R/W
0
0 = Normal operation.
5B Symbol/
1 = 5-bit Symbol Mode (Bypass encoder/decoder);
RXD<4:0> symbol data is not aligned.
(100BASE-X only)
4B Nibble
Note 4
0 = 4-bit Nibble Mode (Normal operation).
1 = Bypass transmit scrambler and receive descrambler.
0 = Normal operation (scrambler and descrambler enabled).
Scrambler
19.3
R/W
Note 5
In FX mode, the LXT970A automatically bypasses the Scrambler.
Selecting Scrambler bypass in FX mode causes the LXT970A to also
bypass the 4B/5B encoder and enable Symbol mode MII operation.
(100BASE-X only)
1. R/W = Read/Write
2. The default value of bit 19.13 is determined by pin MF1.
3. If auto-negotiation is disabled, the default value of bit 19.8 is determined by pin CFG1. If auto-neg is enabled, the default
value of bit 19.8 = 0.
4. The default value of bit 19.4 is determined by pin MF2 Operation.
5. The default value of bit 19.3 is determined by pin MF3 Operation.
6. If auto-negotiation is disabled, default value of bit 19.2 is determined by pin MF4. If auto-negotiation is enabled, default value
of bit 19.2 = 0.
Datasheet
71
INTEL [ INTEL ]
