Fast Ethernet 10/100 Hex Transceiver with Full MII — LXT9763
Figure 1. LXT9763 Block Diagram
RESET
CFG<2:0>
ADD<4:0>
MDIO
MDC
MDINT
Management /
Mode Select
Logic
Global Functions
Clock
Generator
VCC
Pwr Supply
GND
REFCLK
Register Set
TX_ENn
TX PCS
TXDn_<3:0>
TX_ERn
TX_CLKn
Parallel/Serial
Converter
Manchester
10
Encoder
Scrambler
100
& Encoder
Auto
Negotiation
Register
Set
Collision
Detect
OSP
™
Pulse
Shaper
TP
Driver
+
-
+
-
TPFOP
n
TP / Fiber
Out
TPFON
n
ECL
Driver
ED/CFGn_<3:0>
COLn
Clock
Generator
Media
Select
OSP
™
Adaptive EQ with
BaseLine Wander
Cancellation
+
100TX
RX_CLKn
RXDn_<3:0>
RXDVn
CRSn
RX_ERn
RX PCS
Carrier Sense
Data Valid
Error Detect
Serial to
Parallel
Converter
10
Manchester
Decoder
-
+
OSP
™
Slicer
10BT
100FX
TP / Fiber
In
TPFIP
n
TPFIN
n
Decoder &
100
Descrambler
-
+
PORT 0
PORT 1
PORT 2
PORT 3
PORT 4
PORT 5
Per-Port Functions
-
Datasheet
9
INTEL [ INTEL CORPORATION ]
