SMART 5 BOOT BLOCK MEMORY FAMILY
E
When CE# and RP# pins are at V
CC
, the
component enters a CMOS standby mode. Driving
RP# to GND enables a deep power-down mode
which significantly reduces power consumption,
provides write protection, resets the device, and
clears the status register. A reset time (t
PHQV
) is
required from RP# switching high until outputs are
valid. Likewise, the device has a wake time (t
PHEL
)
from RP#-high until writes to the CUI are
recognized. See Section 4.2.
The deep power-down mode can also be used as a
device reset, allowing the flash to be reset along
with the rest of the system. For example, when the
flash memory powers-up, it automatically defaults
to the read array mode, but during a warm system
reset, where power continues uninterrupted to the
system components, the flash memory could
remain in a non-read mode, such as erase.
Consequently, the system Reset signal should be
tied to RP# to reset the memory to normal read
mode upon activation of the Reset signal. This also
provides protection against unwanted command
writes due to invalid system bus conditions during
system reset or power-up/down sequences.
These devices are configurable at power-up for
either byte-wide or word-wide input/output using the
BYTE# pin. Please see Table 2 for a detailed
description of BYTE# operations, especially the
usage of the DQ
15
/A
–1
pin.
These Smart 5 memory products are available in
the 44-lead PSOP (Plastic Small Outline Package),
which is ROM/EPROM-compatible, and the 48-lead
TSOP (Thin Small Outline Package, 1.2 mm thick)
as shown in Figure 1, and 2, respectively.
SmartVoltage technology enables fast factory
programming and low-power designs. Specifically
designed for 5 V systems, Smart 5 components
support read operations at 5 V V
CC
and internally
configure to program/erase at 5 V or 12 V. The 12 V
V
PP
option renders the fastest program and erase
performance which will increase your factory
throughput. With the 5 V V
PP
option, V
CC
and V
PP
can be tied together for a simple 5 V design. In
addition, the dedicated V
PP
pin gives complete data
protection when V
PP
≤
V
PPLK
.
The memory array is asymmetrically divided into
blocks in an asymmetrical architecture to
accommodate microprocessors that boot from the
top (denoted by
-T
suffix) or the bottom (-B suffix)
of the memory map. The blocks include a
hardware-lockable boot block (16,384 bytes), two
parameter blocks (8,192 bytes each) and main
blocks (one block of 98,304 bytes and additional
block(s) of 131,072 bytes). See Figures 4–7 for
memory maps. Each block can be independently
erased and programmed 100,000 times at
commercial temperature or 10,000 times at
extended temperature. Unlike erase operations,
which erase all locations within a block
simultaneously, each byte or word in the flash
memory can be programmed independently of other
memory locations.
The hardware-lockable boot block provides
complete code security for the kernel code required
for system initialization. Locking and unlocking of
the boot block is controlled by WP# and/or RP#
(see Section 3.3 for details).
The system processor interfaces to the flash device
through a Command User Interface (CUI), using
valid command sequences to initiate device
automation. An internal Write State Machine (WSM)
automatically executes the algorithms and timings
necessary for program and erase operations. The
Status Register (SR) indicates the status of the
WSM and whether it successfully completed the
desired program or erase operation.
The Automatic Power Savings (APS) feature
substantially reduces active current when the
device is in static mode (addresses not switching).
In APS mode, the typical I
CCR
current is 1 mA.
2.0
PRODUCT DESCRIPTION
This section describes the pinout and block
architecture of the device family.
2.1
Pin Descriptions
The pin descriptions table details the usage of each
of the device pins.
6
ADVANCE INFORMATION
INTEL [ INTEL CORPORATION ]
