3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
B.5
System Interface Information
Table 25. System Interface Information
Hex
Code
Offset
Length
Description
Addr.
Value
V
V
V
V
logic supply minimum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 BCD volts
CC
1Bh
1Ch
1Dh
1
1B:
--27
--36
--B4
2.7 V
logic supply maximum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 BCD volts
CC
1
1
1C:
1D:
3.3 V
[programming] supply minimum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 HEX volts
PP
11.4 V
[programming] supply maximum program/erase voltage
PP
1Eh
1Fh
1Bh
1
1
1
bits 0–3 BCD 100 mV
bits 4–7 HEX volts
1E:
1F:
1B:
--C6
--05
--27
12.6 V
32 µs
2.7 V
“n” such that typical single word program time-out = 2n µs
V
V
V
V
logic supply minimum program/erase voltage
CC
bits 0–3 BCD 100 mV
bits 4–7 BCD volts
logic supply maximum program/erase voltage
CC
1Ch
1Dh
1
1
bits 0–3 BCD 100 mV
bits 4–7 BCD volts
1C:
1D:
--36
--B4
3.3 V
[programming] supply minimum program/erase voltage
PP
bits 0–3 BCD 100 mV
bits 4–7 HEX volts
11.4 V
[programming] supply maximum program/erase voltage
PP
1Eh
1Fh
1Bh
1
1
1
bits 0–3 BCD 100 mV
bits 4–7 HEX volts
1E:
1F:
1B:
--C6
--05
--27
12.6 V
32 µs
2.7 V
“n” such that typical single word program time-out = 2n µs
V
V
V
logic supply minimum program/erase voltage
CC
bits 0–3 BCD 100 mV
bits 4–7 BCD volts
logic supply maximum program/erase voltage
CC
1Ch
1Dh
1
1
bits 0–3 BCD 100 mV
bits 4–7 BCD volts
1C:
1D:
--36
--B4
3.3 V
[programming] supply minimum program/erase voltage
PP
bits 0–3 BCD 100 mV
bits 4–7 HEX volts
11.4 V
20h
21h
22h
23h
24h
25h
26h
1
1
1
1
1
1
1
“n” such that typical max. buffer write time-out = 2n µs
“n” such that typical block erase time-out = 2n ms
20:
21:
22:
23:
24:
25:
26:
--00
--0A
--00
--04
--00
--03
--00
n/a
1 s
“n” such that typical full chip erase time-out = 2n ms
n/a
“n” such that maximum word program time-out = 2n times typical
“n” such that maximum buffer write time-out = 2n times typical
“n” such that maximum block erase time-out = 2n times typical
“n” such that maximum chip erase time-out = 2n times typical
512 µs
n/a
8 s
NA
Datasheet
55
INTEL [ INTEL ]
