3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
B.6
Device Geometry Definition
n
Table 26. Device Geometry Definition
Code
See Table Below
Offset
Length
Description
27h
28h
1
2
“n” such that device size = 2n in number of bytes
Flash device interface: x8 async x16 async x8/x16 async
28:00,29:00 28:01,29:00 28:02,29:00
27:
28:
29:
2A:
2B:
--01
--00
--00
--00
x16
2Ah
2
“n” such that maximum number of bytes in write buffer = 2n
0
Number of erase block regions within device:
1. x = 0 means no erase blocking; the device erases in “bulk”
2. x specifies the number of device or partition regions with one or
more contiguous same-size erase blocks.
2Ch
2Dh
1
4
2C:
--02
2
3. Symmetrically blocked partitions have one blocking region
4. Partition size = (total blocks) x (individual block size)
Erase Block Region 1 Information
2D:
2E:
2F:
30:
31:
32:
33:
34:
bits 0–15 = y, y+1 = number of identical-size erase blocks
bits 16–31 = z, region erase block(s) size are z x 256 bytes
31h
4
Erase Block Region 2 Information
bits 0–15 = y, y+1 = number of identical-size erase blocks
bits 16–31 = z, region erase block(s) size are z x 256 bytes
Device Geometry Definition
16-Mbit
32-Mbit
Address
–B
–T
–B
–T
27:
28:
29:
2A:
2B:
2C:
2D:
2E:
2F:
30:
31:
32:
33:
34:
--15
--01
--00
--00
--00
--02
--07
--00
--20
--00
--1E
--00
--00
--01
--15
--01
--00
--00
--00
--02
--1E
--00
--00
--01
--07
--00
--20
--00
--16
--01
--00
--00
--00
--02
--07
--00
--20
--00
--3E
--00
--00
--01
--16
--01
--00
--00
--00
--02
--3E
--00
--00
--01
--07
--00
--20
--00
56
Datasheet
INTEL [ INTEL ]
