PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
Figure 27. 16-Bit System to 8-Bit I/O Card: Odd Byte Timing
-REG,
A[25:0]
t
1
-IOIS16
t
2
-CE2
t
3
-CE1
t
4
-IOWR, -IORD
t
5
t
6
D[7:0]
Write Cycle
D[7:0]
Read Cycle
D[15:8]
Read or
Write Cycle
Odd Data
Odd Data
XX
Table 36. DMA Read Cycle Timing (PD6722 only)
(Sheet 1 of 2)
Symbol
t
1
t
2
t
3
t
4
t
5
t
6
Parameter
DRQ (IRQ10) and DACK* (IRQ9) active to DMA cycle begin
-CE[2:1], -REG, -IORD, -OE, and Write Data setup to -IOWR
active
1
Command: -IOWR pulse width
2
Recovery: -IOWR inactive to end of cycle
3
-WAIT active from -IOWR active
-WAIT inactive to -IOWR inactive
2 Tcp
MIN
40
(S
×
Tcp) – 10
(C
×
Tcp) – 10
(R
×
Tcp) – 10
(C – 2)Tcp – 10
MAX
Units
ns
ns
ns
ns
ns
ns
1. The Setup time is determined by the value programmed into the
Setup Timing
register, index 3Ah/3Dh. Using the Timer Set
0 default value of 01h, the setup time would be 70 ns. S = (N
pres
×
N
val
+ 1), see
2. The Command time is determined by the value programmed into the
Command Timing
register, index 3Bh/3Eh. Using the
Timer Set 0 default value of 06h, the Command time would be 270 ns. C = (N
pres
×
N
val
+ 1), see page
3. The Recovery time is determined by the value programmed into the
Recovery Timing
register, index 3Ch/3Fh. Using the
Timer Set 0 default value of 03h, the hold (Recovery) time would be 150 ns. R = (N
pres
×
N
val
+ 1), see page
4. Based on an internal clock period of 40 ns (25 MHz).
116
Datasheet
INTEL [ INTEL CORPORATION ]
