8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
Table 2. 28F800/008B Pin Descriptions
(Continued)
Symbol
WP#
Type
INPUT
Name and Function
WRITE PROTECT:
Provides a method for unlocking the
boot block in a system without a 12V supply.
When WP# is at logic low, the boot block is locked
,
preventing program and erase operations to the boot block. If
a program or erase operation is attempted on the boot block
when WP# is low, the corresponding status bit (bit 4 for
program, bit 5 for erase) will be set in the Status Register to
indicate the operation failed.
When WP# is at logic high, the boot block is unlocked
and
can be programmed or erased.
NOTE:
This feature is overridden and the boot block
unlocked when RP# is at V
HH
. This pin is not available on the
44-lead PSOP package. See Section 3.4 for details on write
protection.
BYTE#
INPUT
BYTE# ENABLE: Not available on 28F008B.
Controls
whether the device operates in the byte-wide mode (x8) or
the word-wide mode (x16). BYTE# pin must be controlled at
CMOS levels to meet the CMOS current specification in the
standby mode.
When BYTE# is at logic low, the byte-wide mode is
enabled,
where data is read and programmed on DQ –DQ
7
0
and DQ
15
/A
–1
becomes the lowest order address that decodes
between the upper and lower byte. DQ –DQ
14
are tri-stated
8
during the byte-wide mode.
When BYTE# is at logic high, the word-wide mode is
enabled,
where data is read and programmed on DQ –DQ
15
.
0
V
CC
V
PP
DEVICE POWER SUPPLY:
5.0V
±
10%, 3.3V
±
0.3V,
2.7V–3.6V
PROGRAM/ERASE POWER SUPPLY:
For erasing
memory array blocks or programming data in each block, a
voltage either of 5V
±
10% or 12V
±
5% must be applied to
this pin. When V
PP
< V
PPLK
all blocks are locked and
protected against Program and Erase commands.
GROUND:
For all internal circuitry.
GND
12
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