8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
1.5
Pin Descriptions
Table 2. 28F800/008B Pin Descriptions
Type
INPUT
Name and Function
ADDRESS INPUTS
for memory addresses. Addresses are
internally latched during a write cycle.
The 28F800 only has
A
0
–A
18
pins, while
the 28F008B has A
0
–A
19
.
ADDRESS INPUT:
When A
9
is at V
HH
the signature mode is
accessed. During this mode, A
0
decodes between the
manufacturer and device IDs. When BYTE# is at a logic low,
only the lower byte of the signatures are read. DQ /A
–1
is a
15
don’t care in the signature mode when BYTE# is low.
DATA INPUTS/OUTPUTS:
Inputs array data on the second
CE# and WE# cycle during a Program command. Inputs
commands to the Command User Interface when CE# and
WE# are active. Data is internally latched during the Write
cycle. Outputs array, Intelligent Identifier and Status Register
data. The data pins float to tri-state when the chip is de-
selected or the outputs are disabled.
DATA INPUTS/OUTPUTS:
Inputs array data on the second
CE# and WE# cycle during a Program command. Data is
internally latched during the Write cycle. Outputs array data.
The data pins float to tri-state when the chip is de-selected or
the outputs are disabled as in the byte-wide mode (BYTE# =
“0”). In the byte-wide mode DQ
15
/A
–1
becomes the lowest
order address for data output on DQ –DQ
7
.
The 28F008B
0
does not include these DQ
8
–DQ
15
pins.
CHIP ENABLE:
Activates the device’s control logic, input
buffers, decoders and sense amplifiers. CE# is active low.
CE# high de-selects the memory device and reduces power
consumption to standby levels. If CE# and RP# are high, but
not at a CMOS high level, the standby current will increase
due to current flow through the CE# and RP# input stages.
OUTPUT ENABLE:
Enables the device’s outputs through
the data buffers during a read cycle. OE# is active low.
WRITE ENABLE:
Controls writes to the Command Register
and array blocks. WE# is active low. Addresses and data are
latched on the rising edge of the WE# pulse.
Symbol
A
0
–A
19
A
9
INPUT
DQ
0
–
DQ
7
INPUT/OUT
PUT
DQ
8
–
DQ
15
INPUT/OUT
PUT
CE#
INPUT
OE#
WE#
INPUT
INPUT
10
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