SMART 3 ADVANCED BOOT BLOCK
When V
PP
< V
PPLK
, the device will only execute the
following commands successfully: Read Array,
Read Status Register, Clear Status Register and
Read Identifier. The device provides standard
EEPROM read, standby and output disable
operations. Manufacturer identification and device
identification data can be accessed through the
CUI. All functions associated with altering memory
contents, namely program and erase, are
accessible via the CUI. The internal Write State
Machine (WSM) completely automates program
and erase operations while the CUI signals the start
of an operation and the status register reports
status. The CUI handles the WE# interface to the
data and address latches, as well as system status
requests during WSM operation.
3.1
Bus Operation
E
DQ
0–7
D
OUT
High Z
High Z
High Z
D
IN
DQ
8–15
D
OUT
High Z
High Z
High Z
D
IN
Smart 3 Advanced Boot Block flash memory
devices read, program and erase in-system via the
local CPU or microcontroller. All bus cycles to or
from the flash memory conform to standard
microcontroller bus cycles. Four control pins dictate
the data flow in and out of the flash component:
CE#, OE#, WE# and RP#. These bus operations
are summarized in Table 3.
Table 3. Bus Operations
(1)
Mode
Read (Array, Status, or
Identifier)
Output Disable
Standby
Reset
Write
Note
2–4
2
2
2, 7
2, 5–7
RP#
V
IH
V
IH
V
IH
V
IL
V
IH
CE#
V
IL
V
IL
V
IH
X
V
IL
OE#
V
IL
V
IH
X
X
V
IH
WE#
V
IH
V
IH
X
X
V
IL
NOTES:
1. 8-bit devices use only DQ[0:7], 16-bit devices use DQ[0:15]
2. X must be V
IL
, V
IH
for control pins and addresses.
3. See
DC Characteristics
for V
PPLK
, V
PP1
, V
PP2
, V
PP3
, V
PP4
voltages.
4. Manufacturer and device codes may also be accessed in read identifier mode (A –A
21
= 0). See Table 4.
1
5. Refer to Table 6 for valid D
IN
during a write operation.
6. To program or erase the lockable blocks, hold WP# at V
IH
.
7. RP# must be at GND
±
0.2 V to meet the maximum deep power-down current specified.
12
PRELIMINARY
INTEL [ INTEL CORPORATION ]
