E
SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE
convenient upgrade from and/or compatibility to
previous 4-Mbit and 8-Mbit Boot Block products.
1.0 INTRODUCTION
The Smart 3 product functions are similar to lower
density products in both command sets and
operation, providing similar pinouts to ease density
upgrades.
This
preliminary
datasheet
contains
the
specifications for the Advanced Boot Block flash
memory family, which is optimized for low power,
portable systems. This family of products features
1.8V–2.2V or 2.7V–3.6V I/Os and a low VCC/VPP
operating range of 2.7V–3.6V for read and
program/erase operations. In addition this family is
capable of fast programming at 12V. Throughout
this document, the term “2.7V” refers to the full
voltage range 2.7V–3.6V (except where noted
otherwise) and “VPP = 12V” refers to 12V ±5%.
Section 1 and 2 provides an overview of the flash
memory family including applications, pinouts and
pin descriptions. Section 3 describes the memory
organization and operation for these products.
The Smart 3 Advanced Boot Block flash memory
features
•
•
•
Enhanced blocking for easy segmentation of
code and data or additional design flexibility
Program Suspend command which permits
program suspend to read
WP# pin to lock and unlock the upper two (or
lower two, depending on location) 4-Kword
blocks
Finally, Sections 4, 5,
operating specifications.
6 and 7 contain the
•
•
VCCQ input for 1.8V–2.2V on all I/Os. See
Figure 1-4 for pinout diagrams and VCCQ
location
1.1
Smart 3 Advanced Boot Block
Flash Memory Enhancements
Maximum program time specification for
improved data storage.
The new 4-Mbit, 8-Mbit, and 16-Mbit Smart 3
Advanced Boot Block flash memory provides a
Table 1. Smart 3 Advanced Boot Block Feature Summary
Feature
VCC Read Voltage
VCCQ I/O Voltage
28F160B3
2.7V– 3.6V
Reference
Table 9, Table 12
Table 9, Table 12
Table 9, Table 12
Table 2
1.8V–2.2V or 2.7V– 3.6V
VPP Program/Erase Voltage
Bus Width
2.7V– 3.6V or 11.4V– 12.6V
16 bit
Speed
120 ns
Table 15
Memory Arrangement
256-Kbit x 16 (4-Mbit), 512-Kbit x 16 (8-Mbit),
1024-Kbit x 16 (16-Mbit)
Blocking (top or bottom)
Eight 4-Kword parameter blocks (4/8/16) &
Seven 32-Kword blocks (4-Mbit)
Section 2.2
Figures 5 and 6
Fifteen 32-Kword blocks (8-Mbit)
Thirty-one 32-Kword main blocks (16-Mbit)
Locking
WP# locks/unlocks parameter blocks
All other blocks protected using VPP switch
Section 3.3
Table 8
Operating Temperature
Program/Erase Cycling
Packages
Extended: –40°C to +85°C
10,000 cycles
Table 9, Table 12
Table 9, Table 12
48-Lead TSOP, 48-Ball µBGA* CSP
Figures 1, 2, 3,
and 4
5
PRELIMINARY
INTEL [ INTEL ]
