SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE
E
1
2
3
4
5
WP#
NC
6
7
A7
8
A4
A
B
A13
A11
A8
VPP
RP#
NC
A17
A6
A14
A10
A12
D14
D15
D7
WE#
A9
A5
A2
C
A15
A3
A1
D
E
A16
D5
D11
D12
D4
D2
D3
D8
CE#
D0
D1
A0
VCCQ
GND
D6
D9
GND
OE#
F
D13
VCC
D10
0580_02
NOTE:
Dotted connections indicate placeholders where there is no solder ball. These connections are reserved for future upgrades.
Routing is not recommended in this area.
Figure 2. 4-Mbit 48-Ball µBGA* Chip Size Package
1
2
3
4
5
WP#
A18
6
7
A7
8
A4
A
B
A13
A11
A8
VPP
RP#
NC
A17
A6
A14
A10
A12
D14
D15
D7
WE#
A9
A5
A2
C
A15
A3
A1
D
E
A16
D5
D11
D12
D4
D2
D3
D8
CE#
D0
D1
A0
VCCQ
GND
D6
D9
GND
OE#
F
D13
VCC
D10
0580_03
NOTE:
Dotted connections indicate placeholders where there is no solder ball. These connections are reserved for future upgrades.
Routing is not recommended in this area.
Figure 3. 8-Mbit 48-Ball µBGA* Chip Size Package
8
PRELIMINARY
INTEL [ INTEL ]
