E
SMART 5 BOOT BLOCK MEMORY FAMILY
CONTENTS
PAGE
PAGE
4.0 DESIGN CONSIDERATIONS ........................24
4.1 Power Consumption ...................................24
4.1.1 Active Power .......................................24
4.1.2 Automatic Power Savings (APS) .........24
4.1.3 Standby Power ....................................25
4.1.4 Deep Power-Down Mode.....................25
4.2 Power-Up/Down Operation.........................25
4.2.1 RP# Connected to System Reset ........25
4.3 Board Design .............................................25
4.3.1 Power Supply Decoupling....................25
4.3.2 VPP Trace on Printed Circuit Boards...25
5.0 ELECTRICAL SPECIFICATIONS..................26
5.1 Absolute Maximum Ratings ........................26
5.2 Operating Conditions..................................26
5.3 Capacitance ...............................................27
5.4 DC Characteristics—Commercial and
Extended Temperature..............................27
5.5 AC Characteristics—Read Operations—
Commercial and Extended Temperature ...31
5.6 Erase and Program Timings—Commercial
and Extended Temperature .......................32
5.7 AC Characteristics—Write Operations—
Commercial and Extended Temperature ...33
6.0 ORDERING INFORMATION..........................35
7.0 ADDITIONAL INFORMATION .......................36
APPENDIX A: Write State Machine: Current-
Next State Chart ..........................................37
APPENDIX B: Product Block Diagram..............38
1.0 INTRODUCTION .............................................5
1.1 New Features in the Smart 5 Memory
Products......................................................5
1.2 Product Overview.........................................5
2.0 PRODUCT DESCRIPTION..............................6
2.1 Pin Descriptions ...........................................6
2.2 Pinouts.........................................................8
2.3 Memory Blocking Organization...................10
2.3.1 One 16-KB Boot Block.........................10
2.3.2 Two 8-KB Parameter Blocks................10
2.3.3 Main Blocks - One 96-KB + Additional
128-KB Blocks....................................10
3.0 PRINCIPLES OF OPERATION .....................13
3.1 Bus Operations ..........................................13
3.1.1 Read....................................................13
3.1.2 Output Disable.....................................14
3.1.3 Standby ...............................................14
3.1.4 Word/Byte Configuration......................14
3.1.5 Deep Power-Down/Reset ....................14
3.1.6 Write....................................................14
3.2 Modes of Operation....................................16
3.2.1 Read Array ..........................................16
3.2.2 Read Identifier .....................................16
3.2.3 Read Status Register ..........................16
3.2.4 Word/Byte Program .............................17
3.2.5 Block Erase .........................................17
3.3 Boot Block Locking ....................................23
3.3.1 V
PP
= V
IL
for Complete Protection .......24
3.3.2 WP# = V
IL
for Boot Block Locking .......24
3.3.3 RP# = V
HH
or WP# = V
IH
for Boot Block
Unlocking ...........................................24
3.3.4 Note for 8-Mbit 44-PSOP Package ......24
ADVANCE INFORMATION
3
INTEL [ INTEL CORPORATION ]
