E
Symbol
A
0
–A
18
A
9
Type
INPUT
INPUT
DQ
0
–DQ
7
DQ
8
–DQ
15
SMART 5 BOOT BLOCK MEMORY FAMILY
Table 2. Pin Descriptions
Name and Function
ADDRESS INPUTS
for memory addresses. Addresses are internally latched
during a write cycle.
28F200: A[0–16], 28F400: A[0–17], 28F800: A[0–18], 28F004: A[0–18]
ADDRESS INPUT:
When A
9
is at V
HH
the signature mode is accessed. During
this mode, A
0
decodes between the manufacturer and device IDs. When BYTE#
is at a logic low, only the lower byte of the signatures are read. DQ
15
/A
–1
is a
don’t care in the signature mode when BYTE# is low.
INPUT/
DATA INPUTS/OUTPUTS:
Inputs array data on the second CE# and WE# cycle
OUTPUT during a Program command. Inputs commands to the Command User Interface
when CE# and WE# are active. Data is internally latched during the write cycle.
Outputs array, intelligent identifier and status register data. The data pins float to
tri-state when the chip is de-selected or the outputs are disabled.
INPUT/
DATA INPUTS/OUTPUTS:
Inputs array data on the second CE# and WE# cycle
OUTPUT during a Program command. Data is internally latched during the write cycle.
Outputs array data. The data pins float to tri-state when the chip is de-selected or
the outputs are disabled as in the byte-wide mode (BYTE# = “0”). In the byte-wide
mode DQ
15
/A
–1
becomes the lowest order address for data output on DQ
0
–DQ
7
.
Not applicable to 28F004B5.
INPUT
CHIP ENABLE:
Activates the device’s control logic, input buffers, decoders and
sense amplifiers. CE# is active low. CE# high de-selects the memory device and
reduces power consumption to standby levels. If CE# and RP# are high, but not
at a CMOS high level, the standby current will increase due to current flow
through the CE# and RP# input stages.
OUTPUT ENABLE:
Enables the device’s outputs through the data buffers during
a read cycle. OE# is active low.
WRITE ENABLE:
Controls writes to the command register and array blocks. WE#
is active low. Addresses and data are latched on the rising edge of the WE#
pulse.
RESET/DEEP POWER-DOWN:
Uses three voltage levels (V
IL
, V
IH
, and V
HH
) to
control two different functions: reset/deep power-down mode and boot block
unlocking. It is backwards-compatible with the BX/BL/BV products.
When RP# is at logic low, the device is in reset/deep power-down mode,
which puts the outputs at High-Z, resets the Write State Machine, and draws
minimum current.
When RP# is at logic high, the device is in standard operation.
When RP#
transitions from logic-low to logic-high, the device defaults to the read array mode.
When RP# is at V
HH
, the boot block is unlocked
and can be programmed or
erased. This overrides any control from the WP# input.
CE#
OE#
WE#
INPUT
INPUT
RP#
INPUT
ADVANCE INFORMATION
7
INTEL [ INTEL CORPORATION ]
