8XC196KB/8XC196KB16
PROCESS INFORMATION
This device is manufactured on P629.0 and 629.1, a
CHMOS III-E process. Additional process and reli-
ability information is available in
the
Intel ®Quality
System Handbook:
http://developer.intel.com/design/quality/quality.htm
Table 2. 8XC196KB Memory Map
Description
External Memory or I/O
Internal ROM/EPROM or External
Memory (Determined by EA)
Reserved. Must contain FFH.
(Note 5)
Upper Interrupt Vectors
ROM/EPROM Security Key
Reserved. Must contain FFH.
(Note 5)
Address
0FFFFH
04000H
3FFFH
2080H
207FH
2040H
203FH
2030H
202FH
2020H
201FH
201AH
2019H
2018H
2017H
2014H
2013H
2000H
1FFFH
1FFEH
1FFDH
0100H
00FFH
0018H
0017H
0000H
NOTE:
1. EPROMs are available as One Time Programmable
(OTPROM) only.
270909 – 2
Reserved. Must Contain 20H.
(Note 5)
CCB
Reserved. Must contain FFH.
(Note 5)
Lower Interrupt Vectors
Figure 2. The 8XC196KB Nomenclature
Table 1. Thermal Characteristics
Package
Type
PLCC
QFP
Port 3 and Port 4
θ
ja
θ
jc
35
°
C/W
70
°
C/W
13
°
C/W
4
°
C/W
External Memory
232 Bytes Register RAM (Note 1)
CPU SFR’s (Notes 1, 3)
All thermal impedance data is approximate for static air
conditions at 1W of power dissipation. Values will change
depending on operation conditions and application. See
the Intel
Packaging Handbook
(order number 240800) for a
description of Intel’s thermal impedance test methodology.
NOTES:
1. Code executed in locations 0000H to 00FFH will be
forced external.
2. Reserved memory locations must contain 0FFH unless
noted.
3. Reserved SFR bit locations must contain 0.
4. Refer to 8XC196KB quick reference for SFR descrip-
tions.
5.
WARNING:
Reserved memory locations must not be
written or read. The contents and/or function of these lo-
cations may change with future revisions of the device.
Therefore, a program that relies on one or more of these
locations may not function properly.
3
INTEL [ INTEL CORPORATION ]
