8XC196KB/8XC196KB16
PIN DESCRIPTIONS
(Continued)
Symbol
Port 0
Port 1
Port 2
Ports 3 and 4
HOLD
HLDA
BREQ
TxD
RxD
EXTINT
T2CLK
T2RST
PWM
T2UP-DN
T2CAPTURE
PMODE
Name and Function
8-bit high impedance input-only port. Three pins can be used as digital inputs and/or as
analog inputs to the on-chip A/D converter.
8-bit quasi-bidirectional I/O port. These pins are shared with HOLD, HLDA and BREQ.
8-bit multi-functional port. All of its pins are shared with other functions in the 87C196KB.
Pins P2.6 and P2.7 are quasi-bidirectional.
8-bit bidirectional I/O ports with open drain outputs. These pins are shared with the
multiplexed address/data bus, which has strong internal pullups.
Bus Hold input requesting control of the bus. Enabled by setting WSR.7.
Bus Hold acknowledge output indicating release of the bus. Enabled by setting WSR.7.
Bus Request output activated when the bus controller has a pending external memory
cycle. Enabled by setting WSR.7.
The TxD pin is used for serial port transmission in Modes 1, 2 and 3. In Mode 0 the pin is
used as the serial clock output.
Serial Port Receive pin used for serial port reception. In Mode 0 the pin functions as input or
output data.
A rising edge on the EXTINT pin will generate an external interrupt.
The T2CLK pin is the Timer2 clock input or the serial port baud rate generator input.
A rising edge on the T2RST pin will reset Timer2.
The pulse width modulator output.
The T2UPDN pin controls the direction of Timer2 as an up or down counter.
A rising edge on P2.7 will capture the value of Timer2 in the T2CAPTURE register.
Programming Mode Select. Determines the EPROM programming algorithm that is
performed. PMODE is sampled after a chip reset and should be static while the part is
operating.
Slave ID Number. Used to assign each slave a pin of Port 3 or 4 to use for passing
programming verification acknowledgement.
Programming ALE Input. Accepted by the 87C196KB when it is in Slave Programming
Mode. Used to indicate that Ports 3 and 4 contain a command/address.
Programming. Falling edge indicates valid data on PBUS and the beginning of
programming. Rising edge indicates end of programming.
Programming Active. Used in the Auto Programming Mode to indicate when programming
activity is complete.
Program Valid. This signal indicates the success or failure of programming in the Auto
Programming Mode. A zero indicates successful programming.
Program Verification. Used in Slave Programming and Auto CLB Programming Modes.
Signal is low after rising edge of PROG if the programming was not successful.
Auto Increment. Active low signal indicates that the auto increment mode is enabled. Auto
Increment will allow reading or writing of sequential EPROM locations without address
transactions across the PBUS for each read or write.
Address/Command/Data Bus. Used to pass commands, addresses, and data to and from
slave mode 87C196KBs. Used by chips in Auto Programming Mode to pass command,
addresses and data to slaves. Also used in the Auto Programming Mode as a regular
system bus to access external memory. Should have pullups to V
CC
when used in slave
programming mode.
7
SID
PALE
PROG
PACT
PVAL
PVER
AINC
Ports 3
and 4
(Programming
Mode)
INTEL [ INTEL CORPORATION ]
