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CA3081 参数 Datasheet PDF下载

CA3081图片预览
型号: CA3081
PDF下载: 下载PDF文件 查看货源
内容描述: 通用大电流NPN晶体管阵列 [General Purpose High Current NPN Transistor Arrays]
分类和应用: 晶体晶体管
文件页数/大小: 6 页 / 151 K
品牌: INTERSIL [ INTERSIL CORPORATION ]
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CA3081, CA3082
Absolute Maximum Ratings
T
A
= 25
o
C
Collector-to-Emitter Voltage (V
CEO
) . . . . . . . . . . . . . . . . . . . . . .16V
Collector-to-Base Voltage (V
CBO
) . . . . . . . . . . . . . . . . . . . . . . . 20V
Collector-to-Substrate Voltage (V
CIO
, Note 1) . . . . . . . . . . . . . 20V
Emitter-to-Base Voltage (V
EBO
) . . . . . . . . . . . . . . . . . . . . . . . . . 5V
Collector Current (I
C
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA
Base Current (I
B
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
Thermal Information
Thermal Resistance (Typical, Note 2)
θ
JA
(
o
C/W)
θ
JC
(
o
C/W)
CERDIP Package. . . . . . . . . . . . . . . . .
115
45
PDIP Package . . . . . . . . . . . . . . . . . . .
100
N/A
SOIC Package . . . . . . . . . . . . . . . . . . .
190
N/A
Maximum Power Dissipation (Any One Transistor) . . . . . . . 500mW
Maximum Junction Temperature (Ceramic Package). . . . . . . . . 175
o
C
Maximum Junction Temperature (Plastic Package) . . . . . . . .150
o
C
Maximum Storage Temperature Range . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . -55
o
C to 125
o
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. The collector of each transistor of the CA3081 and CA3082 is isolated from the substrate by an integral diode. The substrate must be connected
to a voltage which is more negative than any collector voltage in order to maintain isolation between transistors and provide normal transistor
action. To avoid undesired coupling between transistors, the substrate terminal (5) should be maintained at either DC or signal (AC) ground. A
suitable bypass capacitor can be used to establish a signal ground.
2.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER
For Equipment Design at T
A
= 25
o
C
SYMBOL
V
(BR)CBO
V
(BR)CIO
V
(BR)CEO
V
(BR)EBO
h
FE
TEST CONDITIONS
I
C
= 500µA, I
E
= 0
I
C
= 500µA, I
B
= 0
I
C
= 1mA, I
B
= 0
I
C
= 500µA
V
CE
= 0.5V, I
C
= 30mA
V
CE
= 0.8V, I
C
= 50mA
MIN
20
20
16
5.0
30
40
-
-
-
-
-
-
TYP
60
60
24
6.9
68
70
0.87
0.27
0.4
0.4
-
-
MAX
-
-
-
-
-
-
1.2
0.5
0.7
0.8
10
1.0
UNITS
V
V
V
V
-
-
V
V
V
V
µA
µA
Collector-to-Base Breakdown Voltage
Collector-to-Substrate Breakdown Voltage
Collector-to-Emitter Breakdown Voltage
Emitter-to-Base Breakdown Voltage
DC Forward Current Transfer Ratio
Base-to-Emitter Saturation Voltage (Figure 4)
Collector-to-Emitter Saturation Voltage
CA3081, CA3082
CA3081 (Figure 5)
CA3082 (Figure 5)
Collector Cutoff Current
Collector Cutoff Current
V
BESAT
V
CESAT
I
C
= 30mA, I
B
= 1mA
I
C
= 30mA, I
B
= 1mA
I
C
= 50mA, I
B
= 5mA
I
C
= 50mA, I
B
= 5mA
I
CEO
I
CBO
V
CE
= 10V, I
B
= 0
V
CB
= 10V, I
E
= 0
Typical Read - Out Driver Applications
V
P
0V
V+
1/7 CA3082
(COMMON COLLECTOR)
R (NOTE)
LIGHT EMITTING DIODE (LED)
40736R
V+
1 SEGMENT OF INCANDESCENT DISPLAY
(DR2000 SERIES OR EQUIVALENT)
FROM
DECODER
1/7 CA3081
(COMMON EMITTER)
NOTE:
The Resistance for R is determined by the relationship:
V
P
V
BE
V
F
(
LED
)
R
= ------------------------------------------------------
-
I
(
LED
)
R
=
0 for V
P
=
V
BE
+
V
F
(
LED
)
Where: V
P
= Input Pulse Voltage
V
F
= Forward Voltage Drop Across the Diode
FIGURE 1. SCHEMATIC DIAGRAM SHOWING ONE
TRANSISTOR OF THE CA3081 DRIVING ONE
SEGMENT OF AN INCANDESCENT DISPLAY
FIGURE 2. SCHEMATIC DIAGRAM SHOWING ONE
TRANSISTOR OF THE CA3082 DRIVING A LIGHT
EMITTING DIODE (LED)
2