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CA3081 参数 Datasheet PDF下载

CA3081图片预览
型号: CA3081
PDF下载: 下载PDF文件 查看货源
内容描述: 通用大电流NPN晶体管阵列 [General Purpose High Current NPN Transistor Arrays]
分类和应用: 晶体晶体管
文件页数/大小: 6 页 / 151 K
品牌: INTERSIL [ INTERSIL CORPORATION ]
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CA3081, CA3082
Small Outline Plastic Packages (SOIC)
N
INDEX
AREA
E
-B-
1
2
3
SEATING PLANE
-A-
D
-C-
A
h x 45
o
H
0.25(0.010) M
B M
M16.15
(JEDEC MS-012-AC ISSUE C)
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
INCHES
SYMBOL
A
L
MILLIMETERS
MIN
1.35
0.10
0.33
0.19
9.80
3.80
MAX
1.75
0.25
0.51
0.25
10.00
4.00
NOTES
-
-
9
-
3
4
-
-
5
6
7
8
o
-
Rev. 0 12/93
MIN
0.0532
0.0040
0.013
0.0075
0.3859
0.1497
MAX
0.0688
0.0098
0.020
0.0098
0.3937
0.1574
A1
B
C
D
α
µ
A1
0.10(0.004)
C
E
e
H
h
L
N
e
B
0.25(0.010) M
C A M
B S
0.050 BSC
0.2284
0.0099
0.016
16
0
o
8
o
0.2440
0.0196
0.050
1.27 BSC
5.80
0.25
0.40
16
0
o
6.20
0.50
1.27
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
α
5