82C59A
Pinouts
82C59A (PDIP, CERDIP, SOIC)
TOP VIEW
CS 1
WR 2
RD 3
D7 4
D6 5
D5 6
D4 7
D3 8
D2 9
D1 10
D0 11
CAS 0 12
CAS 1 13
GND 14
28 V
CC
27 A0
26 INTA
25 IR7
24 IR6
23 IR5
22 IR4
21 IR3
20 IR2
19 IR1
18 IR0
17 INT
16 SP/EN
15 CAS 2
D6 5
D5 6
D4 7
D3 8
D2 9
D1 10
D0 11
12
CAS 0
13
CAS 1
14
GND
15
CAS 2
16
SP/ EN
17
INT
18
IR0
82C59A (PLCC, CLCC)
TOP VIEW
INTA
26
25 IR7
24 IR6
23 IR5
22 IR4
21 IR3
20 IR2
19 IR1
V
CC
28
INT
WR
RD
CS
D7
A0
27
4
3
2
1
PIN
D7 - D0
RD
WR
A0
CS
CAS 2 - CAS 0
SP/EN
INT
INTA
IR0 - IR7
DESCRIPTION
Data Bus (Bidirectional)
Read Input
Write Input
Command Select Address
Chip Select
Cascade Lines
Slave Program Input Enable
Interrupt Output
Interrupt Acknowledge Input
Interrupt Request Inputs
Functional Diagram
INTA
D
7
-D
0
DATA
BUS
BUFFER
CONTROL LOGIC
RD
WR
A
0
CS
READ/
WRITE
LOGIC
IN -
SERVICE
REG
(ISR)
PRIORITY
RESOLVER
INTERRUPT
REQUEST
REG
(IRR)
IR0
IR1
IR2
IR3
IR4
IR5
IR6
IR7
CAS 0
CAS 1
CAS 2
SP/EN
CASCADE
BUFFER
COMPARATOR
INTERNAL BUS
INTERRUPT MASK REG
(IMR)
FIGURE 1.
4-2
INTERSIL [ INTERSIL CORPORATION ]
