82C59A
ADDRESS BUS (16)
CONTROL BUS
I/OR
DATA BUS (8)
I/OW
INT
INTA
CS
CASCADE
LINES
CAS 0
CAS 1
CAS 2
SP/EN
A
0
D
7
- D
0
82C59A
RD
WR
INT
INTA
IRQ
7
IRQ
6
IRQ
5
IRQ
4
IRQ
3
IRQ
2
IRQ
1
IRQ
0
SLAVE PROGRAM/
ENABLE BUFFER
INTERRUPT
REQUESTS
FIGURE 5. 82C59A STANDARD SYSTEM BUS INTERFACE
6. This completes the interrupt cycle. In the AEOI mode, the
ISR bit is reset at the end of the second INTA pulse. Oth-
erwise, the ISR bit remains set until an appropriate EOI
command is issued at the end of the interrupt subroutine.
If no interrupt request is present at step 4 of either sequence
(i.e., the request was too short in duration), the 82C59A will
issue an interrupt level 7. If a slave is programmed on IR bit
7, the CAS lines remain inactive and vector addresses are
output from the master 82C59A.
CONTENT OF SECOND INTERRUPT VECTOR BYTE
IR
D7
7
6
5
4
3
A7
A7
A7
A7
A7
A7
A7
A7
D6
A6
A6
A6
A6
A6
A6
A6
A6
D5
A5
A5
A5
A5
A5
A5
A5
A5
INTERVAL = 4
D4
1
1
1
1
0
0
0
0
D3
1
1
0
0
1
1
0
0
D2
1
0
1
0
1
0
1
0
D1
0
0
0
0
0
0
0
0
D0
0
0
0
0
0
0
0
0
Interrupt Sequence Outputs
8080, 8085 Interrupt Response Mode
This sequence is timed by three INTA pulses. During the first
lNTA pulse, the CALL opcode is enabled onto the data bus.
First Interrupt Vector Byte Data: Hex CD
D7
Call Code
1
D6
1
D5
0
D4
0
D3
1
D2
1
D1
0
D0
1
2
1
0
IR
INTERVAL = 8
D7
D6
A6
A6
A6
A6
A6
A6
A6
A6
DS
1
1
1
1
0
0
0
0
D4
1
1
0
0
1
1
0
0
D3
1
0
1
0
1
0
1
0
D2
0
0
0
0
0
0
0
0
D1
0
0
0
0
0
0
0
0
D0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
A7
A7
A7
A7
A7
A7
A7
A7
During the second INTA pulse, the lower address of the
appropriate service routine is enabled onto the data bus.
When interval = 4 bits, A5 - A7 are programmed, while
A0 - A4 are automatically inserted by the 82C59A. When
interval = 8, only A6 and A7 are programmed, while A0 - A5
are automatically inserted.
During the third INTA pulse, the higher address of the appro-
priate service routine, which was programmed as byte 2 of the
initialization sequence (A8 - A15), is enabled onto the bus.
4-6
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