DG506A, DG507A, DG508A, DG509A
Functional Diagrams
DG506A
S
1
S
2
S
3
S
4
S
5
S
6
S
7
S
8
D
S
9
S
10
S
11
S
12
S
13
S
14
S
15
S
16
A
0
A
1
A
2
A
3
EN
ADDRESS DECODER
1 OF 16
ENABLE
1 OF 4
S
1B
S
2B
S
3B
S
4B
S
5B
S
6B
S
7B
S
8B
A
0
A
1
A
2
EN (ENABLE INPUT)
D
B
ADDRESS DECODER
1 OF 8
ENABLE
1 OF 2
S
1A
S
2A
S
3A
S
4A
S
5A
S
6A
S
7A
S
8A
D
A
DG507A
4 Line Binary Address Inputs
(0 0 0 1) and EN = 5V
Above example shows channel 2 turned ON.
DG508A
S
1
S
2
S
3
S
4
S
5
S
6
S
7
S
8
A
0
A
1
A
2
EN (ENABLE INPUT)
D
ADDRESS DECODER
1 OF 8
3 Line Binary Address Inputs
(0 0 0) and EN = 5V
Above example shows channels 1
A
and 1
B
turned ON.
DG509A
S
1A
S
2A
S
3A
S
4A
S
1B
S
2B
S
3B
S
4B
D
B
D
A
3 Line Binary Address Inputs
(1 0 1) and EN = 1
Above example shows channel 6 turned ON.
2 Line Binary Address Inputs
(0 0) and EN = 1
Above example shows channels 1
A
and 1
B
turned ON.
Schematic Diagram
V+
V+
S
X
LOGIC TRIP
POINT REF
GND
LOGIC A
X
INPUT OR EN
V-
LOGIC INTERFACE
AND LEVEL SHIFTER
DECODER
+
-
A
X
D
X
TYPICAL
SWITCH
3
INTERSIL [ INTERSIL CORPORATION ]
