HFA3824A
External Interfaces
There are three primary digital interface ports for the
HFA3824A that are used for configuration and during normal
operation of the device. These ports are:
• The
TX Port,
which is used to accept the data that needs
to be transmitted from the network processor.
• The
RX Port,
which is used to output the received
demodulated data to the network processor.
• The
Control Port,
which is used to configure, write and/or
read the status of the internal HFA3824A registers.
In addition to these primary digital interfaces the device
includes a byte wide parallel
Test Port
which can be config-
ured to output various internal signals and/or data (i.e., PN
acquisition indicator, Correlator magnitude output etc.). The
device can also be set into various power consumption
modes by external control. The HFA3824A contains three
Analog to Digital (A/D) converters. The analog interfaces to
the HFA3824A include, the In phase (I) and quadrature (Q)
data component inputs, and the RF signal strength indicator
input. A reference voltage divider is also required external to
the device.
HFA3824A
ANALOG
INPUTS
A/D
REFERENCE
POWER
DOWN
SIGNALS
TEST
PORT
8
I (ANALOG)
TXD
Q (ANALOG)
RSSI (ANALOG) TXCLK
TX_RDY
V
REFN
RXD
V
REFP
RXC
MD_RDY
TX_PE
CS
RX_PE
SD
RESET
SCLK
R/W
TEST
AS
Control Port
The serial control port is used to serially write and read data
to/from the device. The serial control port is used to serially
write and read data to/from the device. This serial port can
operate up to a 11MHz rate or the maximum master clock
rate of the device, MCLK (whichever is lower). MCLK must
be running and RESET inactive during programming. This
port is used to program and to read all internal registers. The
first 8 bits always represent the address followed immedi-
ately by the 8 data bits for that register. The two LSBs of
address are don’t care. The serial transfers are accom-
plished through the serial data pin (SD). SD is a bidirectional
serial data bus. An Address Strobe (AS), Chip Select (CS),
and Read/Write (R/W) are also required as handshake sig-
nals for this port. The clock used in conjunction with the
address and data on SD is SCLK. This clock is provided by
the external source and it is an input to the HFA3824A. The
timing relationships of these signals are illustrated on Figure
3 and 4. AS is active high during the clocking of the address
bits. R/W is high when data is to be read, and low when it is
to be written. CS must be sampled high to initialize state
machine. CS must be active (low) during the entire data
transfer cycle. CS selects the device. The serial control port
operates asynchronously from the TX and RX ports and it
can accomplish data transfers independent of the activity at
the other digital or analog ports. CS does not effect the TX or
RX operation of the device; impacting only the operation of
the Control port. The HFA3824A has 57 internal registers
that can be configured through the control port. These regis-
ters are listed in the Configuration and Control Internal Reg-
ister table. Table 1 lists the configuration register number, a
brief name describing the register, and the HEX address to
access each of the registers. The type indicates whether the
corresponding register is Read only (R) or Read/Write
(R/W). Some registers are two bytes wide as indicated on
the table (high and low bytes).
TX_PORT
RX_PORT
CONTROL_PORT
FIGURE 2. EXTERNAL INTERFACE
7
SCLK
FIRST ADDRESS BIT
6
5
4
3
2
1
0
FIRST DATABIT OUT
7
6
5
4
3
2
1
0
7
6
5
4
SD
AS
R/W
CS
7
MSB
6
5
4
3
2
1
7
MSB
6
5
4
3
2
1
0
LSB
ADDRESS IN
DATA OUT
NOTES:
1. These diagrams assume the HFA3824A always uses the rising edge of SCLK, the controller the falling edge.
2. The CS is a synchronous interface in reference to SCLK. There is at least one clock required before CS transitions to its active state.
3. If the SD bus is shared, then R/W should be left Low, or CS High, to avoid bus conflicts.
FIGURE 3. CONTROL PORT READ TIMING
2-105
INTERSIL [ INTERSIL CORPORATION ]
