HFA3824A
7
SCLK
SD
AS
7
MSB
6
5
4
3
2
1
0
7
MSB
6
5
4
3
2
1
0
LSB
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
ADDRESS IN
DATA IN
R/W
CS
NOTE: Using falling edge SCLK to generate address/control and data.
FIGURE 4. CONTROL PORT WRITE TIMING
TABLE 1. CONFIGURATION AND CONTROL INTERNAL REGISTER LIST
CONFIGURATION
REGISTER
CR0
CR1
CR2
CR3
CR4
CR5
CR6
CR7
CR8
CR9
CR10
CR11
CR12
CR13
CR14
CR15
CR16
CR17
CR18
CR19
CR20
CR21
CR22
CR23
CR24
CR25
CR26
CR27
CR28
CR29
NAME
Modem Config. Register A
Modem Config. Register B
Modem Config. Register C
Modem Config. Register D
Internal Test Register A
Internal Test Register B
Internal Test Register C
Modem Status Register A
Modem Status Register B
I/O Definition Register
RSSI Value Register
ADC_CAL_POS Register
ADC_CAL_NEG Register
TX_Spread Sequence (High)
TX_Spread Sequence (Low)
Scramble_Seed
Scramble_Tap (RX and TX)
Reserved
Reserved
RSSI_TH
RX_Spread Sequence (High)
RX_Spread Sequence (Low)
RX_SQ1_ ACQ (High) Threshold
RX-SQ1_ ACQ (Low) Threshold
RX-SQ1_ ACQ (High) Read
RX-SQ1_ ACQ (Low) Read
RX-SQ1_ Data (High) Threshold
RX-SQ1-SQ1_ Data (Low) Threshold
RX-SQ1_ Data (High) Read
RX-SQ1_ Data (Low) Read
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R/W
R/W
R
R
REGISTER
ADDRESS HEX
00
04
08
0C
10
14
18
1C
20
24
28
2C
30
34
38
3C
40
44
48
4C
50
54
58
5C
60
64
68
6C
70
74
2-106
INTERSIL [ INTERSIL CORPORATION ]
