IS41LV16100B
AC TEST CONDITIONS
Output load: One TTL Load and 50 pF (V
DD
= 3.3V ±10%)
Input timing reference levels:
Output timing reference levels:
V
IH
= 2.0V, V
IL
= 0.8V (V
DD
= 3.3V ±10%)
V
OH
= 2.0V, V
OL
= 0.8V
ISSI
®
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight
RAS
refresh cycle (RAS-Only or CBR) before proper device
operation is assured. The eight
RAS
cycles wake-up should be repeated any time the t
REF
refresh requirement is exceeded.
2. V
IH
(MIN) and V
IL
(MAX) are reference levels for measuring timing of input signals. Transition times, are measured between V
IH
and
V
IL
(or between V
IL
and V
IH
) and assume to be 1 ns for all inputs.
3. In addition to meeting the transition rate specification, all input signals must transit between V
IH
and V
IL
(or between V
IL
and V
IH
) in a
monotonic manner.
4. If
CAS
and
RAS
= V
IH
, data output is High-Z.
5. If
CAS
= V
IL
, data output may contain data from the last valid READ cycle.
6. Measured with a load equivalent to one TTL gate and 50 pF.
7. Assumes that t
RCD
≤
t
RCD
(MAX). If t
RCD
is greater than the maximum recommended value shown in this table, t
RAC
will increase
by the amount that t
RCD
exceeds the value shown.
8. Assumes that t
RCD
≤
t
RCD
(MAX).
9. If
CAS
is LOW at the falling edge of
RAS,
data out will be maintained from the previous cycle. To initiate a new cycle and clear the data
output buffer,
CAS
and
RAS
must be pulsed for t
CP
.
10. Operation with the t
RCD
(MAX) limit ensures that t
RAC
(MAX) can be met. t
RCD
(MAX) is specified as a reference point only; if t
RCD
is
greater than the specified t
RCD
(MAX) limit, access time is controlled exclusively by t
CAC
.
11. Operation within the t
RAD
(MAX) limit ensures that t
RCD
(MAX) can be met. t
RAD
(MAX) is specified as a reference point only; if t
RAD
is
greater than the specified t
RAD
(MAX) limit, access time is controlled exclusively by t
AA
.
12. Either t
RCH
or t
RRH
must be satisfied for a READ cycle.
13. t
OFF
(MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to V
OH
or V
OL
.
14. t
WCS
, t
RWD
, t
AWD
and t
CWD
are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If t
WCS
≤
t
WCS
(MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If t
RWD
≤
t
RWD
(MIN), t
AWD
≤
t
AWD
(MIN) and t
CWD
≤
t
CWD
(MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from
the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until
CAS
and
RAS
or
OE
go back
to V
IH
) is indeterminate.
OE
held HIGH and
WE
taken LOW after
CAS
goes LOW result in a LATE WRITE (OE-controlled) cycle.
15. Output parameter (I/O) is referenced to corresponding
CAS
input, I/O0-I/O7 by
LCAS
and I/O8-I/O15 by
UCAS.
16. During a READ cycle, if
OE
is LOW then taken HIGH before
CAS
goes HIGH, I/O goes open. If
OE
is tied permanently LOW, a LATE
WRITE or READ-MODIFY-WRITE is not possible.
17. Write command is defined as
WE
going low.
18. LATE WRITE and READ-MODIFY-WRITE cycles must have both t
OD
and t
OEH
met (OE HIGH during WRITE cycle) in order to ensure
that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if
CAS
remains LOW and
OE
is taken back to LOW after t
OEH
is met.
19. The I/Os are in open during READ cycles once t
OD
or t
OFF
occur.
20. The first
χCAS
edge to transition LOW.
21. The last
χCAS
edge to transition HIGH.
22. These parameters are referenced to
CAS
leading edge in EARLY WRITE cycles and
WE
leading edge in LATE WRITE or READ-
MODIFY-WRITE cycles.
23. Last falling
χCAS
edge to first rising
χCAS
edge.
24. Last rising
χCAS
edge to next cycle’s last rising
χCAS
edge.
25. Last rising
χCAS
edge to first falling
χCAS
edge.
26. Each
χCAS
must meet minimum pulse width.
27. Last
χCAS
to go LOW.
28. I/Os controlled, regardless
UCAS
and
LCAS.
29. The 3 ns minimum is a parameter guaranteed by design.
30. Enables on-chip refresh and address counters.
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. B
04/13/05
9
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
