IS61C1024
IS61C1024L
AC WAVEFORMS
WRITE CYCLE NO. 1
(
CE
Controlled,
OE
is HIGH or LOW)
(1 )
t
WC
ADDRESS
VALID ADDRESS
ISSI
t
SCE1
t
SCE2
®
t
SA
CE1
t
HA
CE2
WE
t
AW
t
PWE1
t
PWE2
t
HZWE
t
LZWE
HIGH-Z
D
OUT
DATA UNDEFINED
t
SD
D
IN
t
HD
DATA
IN
VALID
CE2_WR1.eps
WRITE CYCLE NO. 2
(
OE
is HIGH During Write Cycle)
(1,2)
t
WC
ADDRESS
VALID ADDRESS
t
HA
OE
CE1
CE2
WE
LOW
HIGH
t
AW
t
PWE1
t
SA
t
HZWE
DATA UNDEFINED
HIGH-Z
t
LZWE
D
OUT
t
SD
D
IN
t
HD
DATA
IN
VALID
CE2_WR2.eps
Notes:
1. The internal write time is defined by the overlap of
CE1
LOW, CE2 HIGH and
WE
LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to
the rising or falling edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if
OE
= V
IH
.
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
SR028-1J
11/03/98
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
