IS61LV10248-10TI 参数 Datasheet PDF下载

IS61LV10248

ISSI

®

AC WAVEFORMS

WRITE CYCLE NO. 2

(1,2)

(WE Controlled:

OE

is HIGH During Write Cycle)

t

WC

ADDRESS

VALID ADDRESS

t

HA

OE

CE

LOW

t

AW

WE

t

PWE1

t

SA

t

HZWE

DATA UNDEFINED

HIGH-Z

t

LZWE

D

OUT

t

SD

D

IN

t

HD

DATA

IN

VALID

CE_WR2.eps

Notes:

1. The internal write time is defined by the overlap of

CE

LOW and

WE

LOW. All signals must be in valid states to initiate a Write, but

any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of

the signal that terminates the Write.

2. I/O will assume the High-Z state if

OE

> V

IH

.

10

Integrated Silicon Solution, Inc. — www.issi.com —

1-800-379-4774

Rev. C

04/13/06